Semiconductor Memory Device Pad Rows and Multiplexer Segmentation
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Solution Overview
Problem
Conventional semiconductor memory devices suffer from deteriorated data input/output characteristics due to the need for a vertical bus connecting first and second input/output multiplexers, which causes additional loading when data passes through.
Innovation Solution
The semiconductor memory device operates without a vertical bus by having first and second input/output multiplexers electrically connected only to their respective rows of pads, allowing each multiplexer to switch data output between pads within its own row based on a data input/output mode control signal, eliminating the need for a connecting bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a vertical bus connects first and second input/output multiplexers to enable data routing between different pad rows, then adaptability to different data input/output modes is improved, but additional loading is introduced that deteriorates data input/output characteristics
Solution Approach 1:
The pad structure is divided into two physically separated rows, with each row independently connected to its own input/output multiplexer. This segmentation eliminates the need for a vertical bus connecting the multiplexers, as each multiplexer only needs to route data within its associated pad row, thereby reducing loading effects while maintaining adaptability to different data input/output modes through independent multiplexer operation
Solution Approach 2:
The patent transitions from a conventional single-row pad structure to a two-row pad structure arranged in different spatial dimensions. By physically separating the pad rows and associating each with its own multiplexer, the design eliminates the vertical bus requirement and its associated loading problems, while still achieving mode adaptability through the coordinated operation of multiple independently connected multiplexers
2Adaptability or versatility
If a vertical bus is used to connect multiplexers for data routing, then data routing flexibility is improved, but frequency characteristic deteriorates due to additional loading
Solution Approach 1:
The data routing function is segmented across two independently connected multiplexers, each associated with a separate pad row. This eliminates the vertical bus that caused loading effects, allowing each multiplexer to operate with reduced loading and thus improved frequency characteristics, while maintaining routing flexibility through the coordinated switching of both multiplexers based on data input/output mode
3Adaptability or versatility
If first and second input/output multiplexers are electrically connected to both rows of pads for mode switching, then adaptability to different modes is improved, but device complexity increases due to additional connections
Solution Approach 1:
The connection architecture is segmented such that the first input/output multiplexer is exclusively connected to the first row of pads and the second input/output multiplexer is exclusively connected to the second row of pads. This segmentation simplifies the connection complexity by eliminating cross-connections between multiplexers and opposite pad rows, while maintaining mode switching capability through the coordinated operation of the two independently connected multiplexers
Data Source
AI summary
A semiconductor memory device includes a first row of pads including a first plurality of data input/output (I/O) pads; a second row of pads including a second plurality of data I/O pads; and a first I/O multiplexer associated with the first row of pads and providing first output data only to at least one data I/O pad of the first row of pads, even after a data I/O mode of the semiconductor memory device has changed. The semiconductor memory device also includes a second I/O multiplexer associated with the second row of pads and providing second output data only to at least one data I/O pad of the second row of pads, even after the data I/O mode has changed.