Memory Device Page Buffer Reservation to Free SRAM for Host Data

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Solution Overview

Problem

The limited size of the high-performance local memory (SRAM) in memory sub-system controllers leads to inefficient and slow performance due to the need for multiple operations to update host data, as non-host data occupies a significant portion of this memory, limiting its capacity for storing host data.

Innovation Solution

A page buffer manager reserves a portion of the memory device's page buffer to store non-host data from the SRAM, freeing up SRAM for host data storage, thereby improving efficiency and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If non-host data is stored in SRAM, then data storage capacity for host data is reduced, but data retention is improved

Engineering Contradiction:
ImproveSRAM capacity for host dataVSAvoidhost data storage capability
Core Design Contradiction:
Quantity of substanceVSLoss of information

Solution Approach 1:

The patent extracts non-host data from SRAM and relocates it to the memory device's page buffer. This separation removes the conflicting element (non-host data) from the SRAM, allowing SRAM to be dedicated to host data storage and eliminating the capacity conflict while maintaining data retention through the page buffer's reserved storage.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The page buffer acts as an intermediary storage medium between SRAM and the memory array. It temporarily holds non-host data that needs to be retained, serving as a mediator that allows SRAM to free up capacity for host data while ensuring non-host data is not lost. The page buffer manager coordinates this data transfer and management.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If SRAM size is increased, then host data storage capacity is improved, but device cost and complexity increase

Engineering Contradiction:
Improvehost data storage capacityVSAvoidSRAM size
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent extends the storage dimension by utilizing the memory device's page buffer as an additional storage location. Instead of increasing SRAM size in the same dimensional space, the solution moves storage capacity to another dimension (the memory device's page buffer), effectively increasing total available storage without adding SRAM complexity or cost.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If page buffer is used for non-host data, then SRAM efficiency is improved, but page buffer availability for memory operations is reduced

Engineering Contradiction:
ImproveSRAM efficiencyVSAvoidpage buffer availability
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The patent implements dynamic management of the page buffer through a page buffer manager that selectively allocates and deallocates buffer space. The page buffer transitions between different states: dedicated to non-host data when needed, available for memory operations when not reserved, and dynamically adjusted based on system requirements. This dynamic allocation resolves the contradiction by making the page buffer adaptable rather than statically assigned.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the allocation parameter of the page buffer dynamically. When non-host data needs retention, the page buffer manager reserves a portion of the page buffer for this purpose. When memory operations require the page buffer, the reservation is released. This parameter change (reserved vs. available state) allows the same resource to serve different functions at different times, improving both SRAM efficiency and page buffer availability.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250244878A1Memory device page buffer management
Publication Date: 2025.07.31 MICRON TECHNOLOGY INC
  • US20250244878A1 patent drawing
  • US20250244878A1 patent drawing
  • US20250244878A1 patent drawing

AI summary

A memory device includes a memory array and control logic, operatively coupled to the memory array, to receive, from a memory sub-system controller, a command related to execution of a memory access operation associated with one or more memory blocks of the memory device. In response to the command, a portion of a page buffer of the memory device is reserved. The memory device causes at least a portion of non-host data received from a high-performance local memory of the memory sub-system controller to be stored in the portion of the page buffer.