Memory Device Block Cipher With Parallel Key Scheduling
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Solution Overview
Problem
Existing cryptographic algorithms for semiconductor memory and storage devices, such as the PRESENT algorithm, incur significant performance overheads due to the generation of round keys prior to encryption or decryption, leading to high latency in cryptographic processes.
Innovation Solution
A method that parallelizes the generation of round keys with encryption and decryption operations, using a key register to track the key state, allowing simultaneous or substantially simultaneous execution of encryption and key modification operations, reducing the number of clock cycles required for both encryption and decryption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If round keys are generated prior to encryption or decryption using traditional cryptographic algorithms, then security strength is improved, but processing time and latency increase significantly
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing the final state of the key register (after all round key generations) as a decryption key. This allows the decryption process to start immediately without waiting for round key generation, as the decryption key is already available. The round keys are generated in parallel with encryption operations, and their final state is captured and stored for immediate use in decryption, eliminating the sequential delay in traditional approaches.
Solution Approach 2:
The patent maintains continuity of useful action by overlapping the generation of round keys with the encryption process. Instead of completing all round key generations before starting encryption, the system generates round keys continuously during encryption, keeping the cryptographic hardware accelerator busy throughout the entire process. This eliminates idle time and ensures continuous productive operation of the encryption/decryption engine.
2Reliability
If cryptographic hardware accelerators implement encryption algorithms with strong security, then security strength is improved, but additional storage area requirements and power consumption increase
Solution Approach 1:
The patent makes the cryptographic hardware accelerator universal by enabling it to perform both encryption and decryption functions using the same hardware resources. The decryption key (final state of key register) serves dual purposes: it is used to generate round keys for encryption and also serves as the starting point for decryption operations. This eliminates the need for separate decryption key storage and reduces overall storage requirements while maintaining full cryptographic functionality.
3Reliability
If round keys are generated sequentially before encryption, then key schedule security is improved, but productivity and throughput decrease
Solution Approach 1:
The patent applies preliminary action by pre-computing the final state of the key register (which contains all round keys generated through the key schedule) and storing it as the decryption key. This allows the system to maintain secure key schedules while enabling parallel processing, as the decryption key is already prepared and can be used immediately when needed, without waiting for sequential round key generation.
Solution Approach 2:
The patent maintains continuous productive action by generating round keys in parallel with encryption operations rather than sequentially before encryption. The key schedule generation continues throughout the encryption process, keeping hardware resources continuously utilized and maximizing throughput while maintaining the security properties of the key schedule.
Data Source
AI summary
A storage device includes multiple memory dies and a controller configured to: (i) encrypt a data block using a key schedule that includes a plurality of round keys generated from an encryption key, the encrypting resulting in an encrypted data block; (ii) during the encrypting, modify a key register during a first plurality of iterations, the key register being updated to a final state of the key register after a final iteration of the plurality of iterations; (iii) store the final state of the key register as a decryption key; and (iv) decrypt the encrypted data block using another key schedule that includes the plurality of round keys that are generated using the decryption key during a second plurality of iterations.