Memory Device Parallel Read Data Output and Cell Counting
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Solution Overview
Problem
Current storage devices face inefficiencies in cache read operations due to sequential performance of data output and cell counting operations, leading to increased overhead and reduced cache read performance.
Innovation Solution
Implementing a memory device with control logic that performs a cell counting operation using a first read voltage and adjusts remaining read voltages based on a read offset table and cell count, allowing for parallel execution of read data output and cell counting, thereby enhancing cache read performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential execution of read data output and cell counting operations is performed, then operational simplicity is maintained, but cache read performance deteriorates due to increased overhead
Solution Approach 1:
The control logic performs the cell counting operation in advance during the read operation phase, before the data output operation completes. By preliminarily counting the number of cells to be read using a first read voltage, the system prepares critical information that will be needed for subsequent operations, enabling the data output operation to proceed with optimized parameters and without waiting for cell counting to complete.
Solution Approach 2:
The patent enables overlapping execution of the data output operation and cell counting operation, eliminating idle time between these operations. While data is being output from previously read cells, the control logic simultaneously performs cell counting on the current read operation, ensuring that processing resources remain continuously utilized and reducing overall overhead time.
2Measurement precision
If cell counting operation is performed before data output operation, then read voltage adjustment accuracy is improved, but overall read operation time increases
Solution Approach 1:
The cell counting operation is performed preliminarily during the read operation phase using a first read voltage, establishing an accurate cell count that informs subsequent voltage adjustments. This preliminary counting ensures measurement precision is achieved without requiring a separate, time-consuming counting phase after data output begins.
Solution Approach 2:
The control logic adjusts read voltages based on the cell count result by referencing a read offset table that maps cell counts to voltage adjustments. This dynamic parameter adjustment optimizes subsequent read operations based on actual cell conditions, improving measurement precision while the overlapping execution maintains time efficiency.
3Productivity
If parallel execution of data output and cell counting operations is implemented, then operational efficiency is improved, but control complexity increases
Solution Approach 1:
The control logic is segmented into distinct functional units: a read operation execution unit that handles voltage application and cell sensing, a cell counting unit that tallies sensed cells, a voltage adjustment unit that modifies read voltages based on cell count, and a data output unit that retrieves stored data. This segmentation allows parallel operation of independent units while maintaining manageable control complexity through modular design.
Solution Approach 2:
The control logic acts as an intermediary that coordinates between the read operation, cell counting, voltage adjustment, and data output operations. It manages the timing and data flow between these parallel operations, ensuring proper synchronization without requiring complex inter-unit communication protocols, thus improving efficiency while controlling complexity.
Data Source
AI summary
A memory device including a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit performs a first read operation using a plurality of read voltages on selected memory cells. The control logic controls the peripheral circuit to perform a cell counting operation, adjust remaining read voltages among the plurality of read voltages based on a read offset table and a cell count which is a result of the cell counting operation, and perform a first read operation on the selected memory cell with the remaining read voltages, in the first read operation. The control logic performs a read data output operation of a second read operation performed before the first read operation and the cell counting operation corresponding to the first read operation in parallel among a plurality of successively performed read operations.