Memory Device Pass and Discharge Transistor Vertical Stacking
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Solution Overview
Problem
The increasing complexity and miniaturization of memory devices require an efficient method for wiring line disposition without increasing the layout area or number of wiring layers, as existing solutions either complicate the layout or increase manufacturing time and cost.
Innovation Solution
A memory device design that includes a pass transistor circuit in one wafer and a discharge transistor circuit in a vertically overlapping second wafer, allowing for the routing of discharge lines in a vertical direction to minimize layout area and reduce the number of wiring layers, thereby reducing manufacturing time and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of wiring lines is increased to support high capacity and high performance, then the memory device functionality is improved, but the layout area and structure complexity increase
Solution Approach 1:
The patent applies vertical stacking of wafers to transition from two-dimensional planar layout to three-dimensional vertical arrangement. The first wafer contains the pass transistor circuit while the second wafer contains the discharge transistor circuit, with discharge lines extending vertically between wafers. This dimensional change allows increased wiring line capacity without proportionally increasing layout area, as vertical space is utilized instead of horizontal expansion.
2Area of stationary object
If the layout area is reduced due to miniaturization, then the memory device size is decreased, but the wiring line disposition becomes more difficult
Solution Approach 1:
By moving the discharge transistor circuit to a vertically stacked second wafer, the patent eliminates the need for complex horizontal routing of discharge lines within a single wafer. The vertical interconnection through discharge lines simplifies the disposition problem, allowing efficient wiring line arrangement in reduced layout area without compromising manufacturability.
Solution Approach 2:
The patent divides the transistor circuit into two separate functional modules across different wafers: the pass transistor circuit in the first wafer and the discharge transistor circuit in the second wafer. This segmentation allows each module to be optimized independently and simplifies the overall wiring line disposition, as discharge lines can be independently routed vertically without interfering with pass transistor connections.
3Quantity of substance
If the number of wiring layers is increased to accommodate more wiring lines, then the wiring capacity is improved, but the manufacturing time and cost increase
Solution Approach 1:
Instead of increasing the number of horizontal wiring layers within a single wafer, the patent utilizes the vertical dimension by stacking wafers. The discharge lines extend vertically from the first wafer to the second wafer, providing additional wiring capacity without requiring additional lateral wiring layers. This approach increases wiring line capacity while avoiding the time-consuming processes associated with creating additional wiring layers.
Data Source
AI summary
A memory device includes a pass transistor circuit included in a first wafer, and configured to transfer an operating voltage to row lines of a memory cell array; and a discharge transistor circuit included in a second wafer that overlaps with the first wafer in a vertical direction, and configured to transfer a discharge voltage to at least one of the row lines.