Memory Device Passive Variable Delay Line Power Reduction
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Solution Overview
Problem
Current memory devices face challenges in reducing power consumption and improving performance due to the presence of delay locked loops (DLLs), which consume significant power and cause timing issues during data transfers between different ranks of memory devices.
Innovation Solution
The solution involves removing the DLL from each memory device and replacing it with a passive variable delay line, allowing the memory controller to manage data transfer timing across multiple memory devices, enabling back-to-back data transfers while reducing power consumption by eliminating phase locking circuitry from individual memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay locked loops (DLLs) are used in each memory device for timing synchronization, then data transfer timing can be maintained, but power consumption increases significantly
Solution Approach 1:
The patent extracts the DLL functionality from individual memory devices and relocates it to the memory controller. The memory controller now manages timing synchronization for multiple memory devices using a single DLL, eliminating the need for separate DLLs in each memory device. This reduces overall power consumption while maintaining timing synchronization across the memory system.
Solution Approach 2:
The patent merges the timing synchronization function from multiple distributed DLLs into a single centralized DLL located in the memory controller. This consolidation allows one DLL to serve multiple memory devices, reducing redundant circuitry and power consumption while maintaining synchronization across all devices.
2Reliability
If DLLs are present in each memory device, then phase locking can be maintained, but device complexity and die size increase
Solution Approach 1:
The phase locking circuitry (DLL) is extracted from each memory device and relocated to the memory controller. This removes complex timing synchronization circuitry from individual memory devices, simplifying their design while centralizing the phase locking function where it can serve multiple devices efficiently.
3Productivity
If back-to-back data transfers between different memory ranks are required, then data transfer speed improves, but timing alignment becomes more difficult
Solution Approach 1:
The memory controller acts as an intermediary that manages timing alignment for back-to-back data transfers between different memory ranks. By centralizing the DLL in the memory controller, it can coordinate and align timing signals across multiple ranks, enabling high-speed back-to-back transfers while maintaining proper synchronization.
Data Source
AI summary
A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.