Semiconductor Memory Device Parallel Bit Testing Flexibility
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Solution Overview
Problem
Conventional semiconductor memory devices are limited in their ability to perform parallel bit testing (PBT) as they are restricted to testing a fixed minimum grouping of cell data, making it difficult to effectively test individual memory cells outside this grouping, especially when defective cells are present.
Innovation Solution
A semiconductor memory device and test method that allows for flexible selection of test data from both input and output data on a bit-by-bit basis, enabling PBT on each bit regardless of defective memory cells, using a controller to configure test data and a test unit to perform the PBT, where one mode signal selects an input data bit for defective cells and others select output data bits, allowing for arbitrary setting of test data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional parallel bit testing is performed on a fixed minimum grouping of cell data, then the test circuitry is simplified and designed for specific data grouping, but the ability to test individual memory cells outside this grouping is restricted
Solution Approach 1:
The test data is segmented into individual bit positions, with each bit position independently selectable from input data or output data through separate mode signals. This allows the PBT to test arbitrary combinations of memory cells by selecting specific bits, rather than being constrained to fixed groupings.
Solution Approach 2:
The test circuitry is made dynamic through mode signals that can change the configuration of test data on a bit-by-bit basis. The same PBT circuit can adapt to test different numbers of memory cells (e.g., 4 cells, 3 cells, or 2 cells) by dynamically selecting which bits come from input data and which from output data, rather than being statically designed for a fixed configuration.
2Reliability
If the PBT is performed on a fixed grouping of cell data, then the test procedure is straightforward, but defective memory cells within the grouping cause the entire test to fail even if other cells are functional
Solution Approach 1:
Each bit position in the test data is treated with local quality - defective cells are identified at the individual cell level rather than grouping level. By selecting which bits to test from input versus output data on a per-bit basis, the system can isolate and identify defective cells locally, allowing functional cells to be tested even when defective cells are present in the overall grouping.
Solution Approach 2:
The test configuration parameters are changed dynamically through mode signals that control the selection of test data sources. By changing which bits are selected from input data versus output data, the system can adapt the test to account for known defective cells, thereby improving detection accuracy for remaining cells while maintaining testing efficiency.
3Adaptability or versatility
If mode signals are used to selectively configure test data from input or output data, then arbitrary setting of test data is enabled, but additional control signals and logic are required
Solution Approach 1:
The mode signals serve multiple functions: they select which bits come from input data versus output data, they determine the number of cells being tested, and they configure the overall test pattern. This multi-functionality reduces the need for separate control mechanisms for each aspect of test configuration, making the added complexity more manageable.
Data Source
AI summary
A semiconductor memory device and related test method are disclosed. Test data is defined from a group of M test bits selected from either input data or corresponding output data. A parallel bit test is then conducted on the test data. The M test bits include N test bits, where N is less than M, selected on a bit by bit basis from the output data, and L test bits, where N+L=M, selected from the input data. The selection of input data may be made in accordance with a don't care case for selected test data.