Semiconductor Memory Device Peak Current Suppression
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Solution Overview
Problem
In NAND flash memory, the increased memory capacity and multilevel data storage lead to slow write speeds due to high peak currents required during write and verify operations, especially when writing data to multiple cells simultaneously, which can result in miswrites and increased write time.
Innovation Solution
A semiconductor memory device with a control circuit that converts data into a format suitable for simultaneous writing to multiple memory cells, using a conversion rule to randomize data patterns and charge only necessary bit lines during verify operations, reducing peak current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is written to multiple cells simultaneously to enhance write performance, then write speed is improved, but peak current increases causing miswrites and reliability degradation
Solution Approach 1:
The patent segments the write operation into multiple phases based on threshold voltage ranges. Instead of writing to all cells simultaneously, the control circuit divides cells into groups (first group with lower threshold voltage range, second group with higher threshold voltage range) and performs write operations sequentially on each group, thereby reducing peak current while maintaining overall write performance
Solution Approach 2:
The patent changes the write voltage parameter dynamically based on the threshold voltage range of the target cells. Different write voltages are applied to different cell groups (e.g., first write voltage for lower threshold range, second write voltage for higher threshold range), optimizing the write operation for each group while controlling overall current consumption
2Loss of time
If the number of cells written simultaneously is increased to reduce write time, then productivity improves, but peak current consumption increases
Solution Approach 1:
The write operation is segmented into multiple concurrent write operations on different cell groups. While individual groups are written with controlled current, multiple groups can be processed in parallel across different bit lines, reducing total write time while maintaining controlled peak current per operation
Solution Approach 2:
The control circuit preliminarily determines the threshold voltage range of target cells before initiating write operations. This preliminary classification allows the system to prepare appropriate write voltages and organize cell groups in advance, enabling efficient sequential writing that reduces both time and current consumption
3Productivity
If write voltage is increased to write high level data to memory cells, then write capability is improved, but miswrite occurs in non-written cells
Solution Approach 1:
The patent applies different write voltages to different cell groups based on their specific threshold voltage ranges. Cells in the first group receive a first write voltage appropriate for their lower threshold range, while cells in the second group receive a second write voltage for their higher threshold range. This localized voltage application ensures each cell receives exactly the voltage needed, preventing miswrites in non-target cells
Solution Approach 2:
By segmenting cells into distinct groups with different threshold voltage characteristics, the patent enables targeted write operations where high voltage is applied only to specific cell groups that require it, rather than applying high voltage to all cells simultaneously. This segmentation prevents harmful effects on cells that don't require high voltage writes
Data Source
AI summary
A memory cell array includes a plurality of memory cells, in which n (n is a natural number equal to 3 or larger) cells are simultaneously written. A control circuit controls the memory cell array. A conversion circuit converts data constituted of k (k is equal to n or smaller, and is a natural number equal to 3 or larger) bits stored in the memory cells into data of h (h is equal to k or larger, and is a natural number equal to 2 or larger) bits on the basis of a conversion rule.