Semiconductor Memory Device Support Pillar Density
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in improving yield due to unevenness in the layered structure of stacked wirings, leading to defects in the lithography process and wiring formation, particularly in the hookup areas where support pillars are less densely arranged.
Innovation Solution
The semiconductor memory device employs a dense arrangement of support pillars in the hookup areas where contacts are not present, matching the density of memory pillars in the cell area, to maintain even subsidence and prevent localized unevenness, thereby improving yield by suppressing defects in wiring formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If support pillars are sparsely arranged in hookup areas, then device complexity is reduced, but manufacturing precision deteriorates due to localized unevenness in layered structure
Solution Approach 1:
The patent applies local quality by differentiating the arrangement density of support pillars based on location: hookup areas have support pillars arranged at the same density as memory pillars to prevent localized unevenness, while other areas may have different densities. This localized adjustment maintains manufacturing precision in critical areas without unnecessarily increasing overall device complexity
2Manufacturing precision
If support pillars are densely arranged in hookup areas, then manufacturing precision is improved by preventing localized unevenness, but device complexity increases
Solution Approach 1:
The patent implements local quality by selectively increasing support pillar density only in hookup areas where contacts are absent, while maintaining appropriate density in other regions. This targeted approach improves manufacturing precision in problematic areas without proportionally increasing overall device complexity
3Ease of manufacture
If support pillars are sparsely arranged, then ease of manufacture is improved, but reliability deteriorates due to defocusing in lithography and wiring formation defects
Solution Approach 1:
The patent applies local quality by concentrating support pillars in hookup areas where they are most needed to prevent lithography defocusing and wiring formation defects, while allowing sparser arrangement in areas where they are less critical. This optimized local distribution maintains reliability without unnecessary manufacturing complexity
Solution Approach 2:
The patent implements preliminary action by pre-positioning support pillars in hookup areas before the lithography and wiring formation processes. This advance preparation prevents localized unevenness that would cause defocusing and wiring defects, ensuring reliable manufacturing outcomes
Data Source
AI summary
A semiconductor memory device according to an embodiment includes a substrate, a first conductive layer, first and second pillars. The substrate includes first to third regions. The first pillars are provided in the first region to penetrate the first conductive layer. The second pillars are provided in the second region or the third region to penetrate the first conductive layer. The second region includes first and second sub-regions. The first sub-region includes a contact corresponding to the first conductive layer. A coverage of the second pillars in the second sub-region is higher than a coverage of the second pillars in the first sub-region and lower than or equal to a coverage of the first pillars in the first region.