Semiconductor Memory Device Plate Line Coupling for Write Disturb
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Ferroelectric memory elements with a 1T-type structure face issues with voltage drops due to oxide films, leading to data interference between memory cells in arrays, known as Write Disturb, where applying voltage to one memory cell affects others.
Innovation Solution
A semiconductor memory device is designed with a first transistor, a capacitor with ferroelectric electrodes, and a second transistor, where the plate line is electrically coupled to the gate electrode of the first transistor and another capacitor electrode, allowing independent voltage control and preventing voltage drops, thus avoiding data interference during writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a 1T-type ferroelectric memory structure with oxide film on semiconductor substrate is used, then the device can be manufactured with standard CMOS processes, but voltage drop occurs due to the oxide film reducing the effective voltage applied to the ferroelectric film
Solution Approach 1:
The patent extracts and removes the oxide film from between the semiconductor substrate and the ferroelectric film, creating a direct contact structure. This eliminates the voltage drop caused by the oxide film while maintaining CMOS compatibility, as the ferroelectric film is now directly applied to the semiconductor substrate surface without the insulating oxide layer in between.
2Quantity of substance
If ferroelectric memory elements are disposed in an array to form a memory cell array, then storage capacity is increased, but data stored in one memory cell is affected by writing or reading operations in other memory cells (Write Disturb)
Solution Approach 1:
The patent introduces a selection transistor for each memory cell that segments the voltage application path. This allows independent control of voltage application to each memory cell, enabling selective writing and reading operations that prevent Write Disturb to unselected cells while maintaining high storage capacity through array configuration.
Solution Approach 2:
The selection transistor acts as an intermediary between the voltage supply and the ferroelectric memory cell. It controls and regulates voltage application, allowing only the selected memory cell to receive the full write voltage while isolating other cells, thus preventing unwanted data rewriting in adjacent or unselected cells.
3Productivity
If voltage is applied to write data in a ferroelectric memory element, then data storage is achieved, but the same voltage is also applied to other ferroelectric memory elements causing their data to be rewritten
Solution Approach 1:
The patent segments the memory cell structure by adding a selection transistor that divides the voltage path. This enables independent control where write voltage can be rapidly applied to the selected cell without affecting others, maintaining high writing speed while preventing unwanted data changes in unselected cells through electrical isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents voltage drops and data interference, enabling stable operation of memory cell arrays by directly applying an electric field to the ferroelectric film without an oxide film, reducing write voltage and preventing data rewriting in unselected cells.
Implementation Method 1
a ferroelectric memory element using an orientation of remanent polarization of a ferroelectric
Implementation Method 2
controls the remanent polarization of the ferroelectric film by an electric field between the gate electrode and the semiconductor substrate
Implementation Method 3
voltage effectively applied to the ferroelectric film is lowered due to a voltage drop caused by the oxide film
Data Source
AI summary
To provide a semiconductor memory device that avoids a voltage drop caused by an oxide film formed on a surface of a semiconductor substrate, and appropriately operates even in a case where a memory cell array is formed. A semiconductor memory device including a first transistor, a capacitor provided with a pair of capacitor electrodes opposed to each other via an insulator, one of the capacitor electrodes being electrically coupled to a gate electrode of the first transistor, a second transistor in which one of a source or a drain is electrically coupled to one of a source or a drain of the first transistor and to another of the capacitor electrodes, and a plate line electrically coupled to the gate electrode of the first transistor and to the one of the capacitor electrodes.