Memory Device Pre-Program Operation Floated Channel Control
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Solution Overview
Problem
The existing memory devices face an increase in time required for subsequent program operations due to excessive erase operations, necessitating a pre-program operation to raise the threshold voltage of memory cells, which in turn requires shortening the time taken for the pre-program operation.
Innovation Solution
A memory device comprising a first select transistor, a plurality of memory cells, and a second select transistor, connected between a source line and a bit line, with a peripheral circuit configured to perform a pre-program operation by applying a program voltage to word lines connected to memory cells with a floated channel, followed by an erase operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase operation is excessively performed on memory blocks, then data storage reliability is improved, but the time required for subsequent program operations increases
Solution Approach 1:
The patent applies preliminary action by performing a pre-program operation before the erase operation. Specifically, the peripheral circuit applies a program voltage to word lines connected to memory cells with a floated channel in advance, which raises the threshold voltage of memory cells before erasure. This preliminary threshold voltage increase prepares the memory cells for faster subsequent program operations after erasing, thus resolving the contradiction by reducing the time penalty of excessive erase operations.
2Productivity
If pre-program operation is performed to increase threshold voltage of memory cells, then the time for subsequent program operations is reduced, but the time required for pre-program operation itself increases
Solution Approach 1:
The patent applies local quality by selectively applying the program voltage only to specific word lines connected to memory cells with floated channels, rather than uniformly to all memory cells. The peripheral circuit identifies and targets only the necessary memory cells for the pre-program operation, applying voltage locally to the required word lines. This selective approach reduces the overall pre-program time while still achieving the necessary threshold voltage increase for the specific memory cells that will be erased, thus resolving the time contradiction.
Solution Approach 2:
The patent applies partial action by performing the pre-program operation on only a subset of memory cells - specifically those with floated channels that will be subsequently erased - rather than all memory cells in the block. This partial pre-programming approach is sufficient to prepare the memory cells for fast subsequent programming after erase, without wasting time on cells that don't require pre-programming, thus reducing the pre-program operation time while maintaining productivity benefits.
3Manufacturing precision
If channel is floated during pre-program operation, then program voltage can be effectively applied to word lines, but the control complexity of the operation increases
Solution Approach 1:
The patent uses the floated channel as an intermediary state that enables effective program voltage application. By floating the channel (isolating it from both source and drain), the patent creates a high-impedance state that allows program voltage to be effectively coupled to the word lines and memory cells. The peripheral circuit controls the timing and duration of this floated state, using it as a mediator to achieve precise voltage application only when needed, thus maintaining manufacturing precision while managing control complexity through structured timing sequences.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively shortens the time required for the pre-program operation, thereby reducing the overall time for subsequent program operations and improving the efficiency of memory device operations.
Implementation Method 1
applying a program voltage to word lines connected to the plurality of memory cells corresponding to a channel that has been floated
Data Source
AI summary
There are provided a memory device and an operating method of the memory device. The memory device includes: a first select transistor, a plurality of memory cells, and a second select transistor, connected between a source line and a bit line; and a peripheral circuit for performing a pre-program operation on the plurality of memory cells and then performing an erase operation on the plurality of memory cells. In the pre-program operation, the peripheral circuit is configured to apply a program voltage to word lines that are connected to the plurality of memory cells corresponding to a channel that has been floated.