Memory Device Bit-Line Precharge Timing for Program Current Control

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Solution Overview

Problem

Existing nonvolatile memory devices face challenges in managing large currents generated during program operations due to the simultaneous increase in voltage of bit and source lines, which can be exacerbated by large numbers of bit lines or high target voltages, necessitating precise control of precharge times to manage current flow effectively.

Innovation Solution

The memory device incorporates a precharge time information storage to determine and store precharge times for bit and source line control signals based on the degree of program operation, and a precharge voltage controller to adjust these times and voltages accordingly, ensuring optimal current management during program operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the voltage of bit and source lines is increased to target voltage simultaneously during program operation, then the program operation can be completed, but a large current is generated inside the nonvolatile memory device

Engineering Contradiction:
Improveprogram operation completionVSAvoidcurrent generation
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent applies preliminary action by increasing the voltage of bit and source lines to target voltage sequentially rather than simultaneously. The controller first increases the voltage of the first bit line to the first target voltage, then subsequently increases the voltage of the second source line to the second target voltage. This staged approach allows the program operation to complete while avoiding the generation of large simultaneous currents that would occur with concurrent voltage increases.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the number of bit lines or magnitude of target voltage is large, then the program operation capacity is increased, but the time to increase voltage to target voltage must be adjusted to control current

Engineering Contradiction:
Improveprogram operation capacityVSAvoidvoltage increase time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements dynamics by making the voltage increase time adjustable based on operational conditions. When the number of bit lines or target voltage magnitude is large, the controller extends the time for increasing voltage to target voltage, allowing current to be controlled within safe limits. This dynamic time adjustment enables the system to maintain high program operation capacity while preventing excessive current generation that would occur with fixed, shorter time intervals.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250231694A1Memory device and operating method thereof
Publication Date: 2025.07.17 SK HYNIX INC
  • US20250231694A1 patent drawing
  • US20250231694A1 patent drawing
  • US20250231694A1 patent drawing

AI summary

A memory device includes a precharge time information storage for storing information on a first precharge time for which a bit line control signal is applied and a second precharge time for which a source line control signal is applied, which are determined according to a degree to which a program operation is performed. The memory device also includes a precharge voltage controller for providing the bit line control signal and the source line control signal respectively to page buffers and a source line driver for a longer precharge time selected from the first precharge time and the second precharge time in the program operation.