Memory Device Preemptive ECC Encode for Partial Word Write Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices with error correction capability require two clock cycles for partial word write operations, significantly slowing down data transfer rates due to the inclusion of ECC decode and correct processes in the critical timing path.
Innovation Solution
The preemptive partial word write approach initiates the ECC encode process before the completion of the ECC decode process, assuming no error, and restarts the encode process if an error is detected, allowing parallel execution of ECC processes and removing the decode and correct processes from the critical timing path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC decode and correct processes are included in the critical timing path for partial word write operations, then data integrity is ensured, but operation time increases significantly
Solution Approach 1:
The patent initiates the ECC encode process before the ECC decode process completes, performing the encode operation in advance based on the assumption that no error will be detected. This preliminary action removes the decode and correct processes from the critical timing path, reducing operation time while maintaining data integrity through the fallback mechanism.
Solution Approach 2:
The patent prepares the ECC encode operation in advance as a preemptive measure, assuming no error will occur. If an error is later detected during decode, the system can restart the encode process with the corrected data. This preliminary anti-action prevents the need to wait for decode completion before initiating encode, thus reducing the critical path time.
2Reliability
If two clock cycles are used for partial word write operations, then ECC decode and correct processes can be completed, but data transfer rate decreases
Solution Approach 1:
The patent performs the ECC encode operation in advance during the first clock cycle, before the ECC decode process completes. This preliminary encode action allows the system to potentially complete the write operation in one cycle if no error is detected, thereby maintaining high data transfer rates while preserving error correction capability.
Solution Approach 2:
The patent enables continuous operation by initiating the ECC encode process without waiting for the decode process to complete. This continuity allows the system to maintain high throughput for the majority of operations (where no error occurs) while still providing error correction when needed, thus improving overall productivity.
3Measurement precision
If ECC encode process waits for ECC decode process completion, then accuracy is ensured, but processing speed decreases
Solution Approach 1:
The patent initiates the ECC encode process before the ECC decode process completes, based on the assumption that no error will be detected. This preliminary encoding action improves processing speed by eliminating the waiting period, while encoding accuracy is maintained through the fallback mechanism that restarts encoding with corrected data if an error is later detected.
Solution Approach 2:
The patent inverts the traditional sequence by assuming no error will occur and proceeding with encode immediately, rather than waiting for decode confirmation. This inversion speeds up processing for the common case (no error) while maintaining accuracy through the corrective fallback path when errors are actually detected.
Data Source
AI summary
A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform a partial word write operation in which an error correction code encode process for the given retrieved word is initiated prior to completion of an error correction code decode process for the given retrieved word based on an assumption that the error correction code decode process will not indicate an error in the given retrieved word. If the error correction code decode process when completed indicates an error in the given retrieved word, the error in the given retrieved word is corrected in the error correction circuitry, and the error correction code encode process is restarted using the corrected word. The error correction code decode process and an associated correct process are thereby removed from a critical timing path of the partial word write operation.