Semiconductor Memory Device Program Disturb Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory devices experience interference and data reliability issues due to program disturb, leading to increased fail bits and reduced reliability, particularly in memory cells closer to the drain selection line.
Innovation Solution
A semiconductor memory device configuration that includes dummy memory cells and memory cells connected in series, with a peripheral circuit controlling data storage such that a first type of data is stored in dummy cells and a second type of data is stored in multiple memory cells, reducing interference and program disturb effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are connected in series to form cell strings for high-density storage, then storage capacity is improved, but interference and program disturb increase causing more fail bits
Solution Approach 1:
The cell string is segmented into multiple regions with different memory cell types: first memory cells (closer to source selection line) store one bit per cell, while second memory cells (closer to drain selection line) store two bits per cell. This segmentation allows optimization of program disturb characteristics in different regions, reducing overall fail bits while maintaining high storage capacity.
Solution Approach 2:
Different memory cells within the same string are assigned different storage capacities based on their position. Memory cells closer to the source selection line store one bit, while those closer to the drain selection line store two bits. This local differentiation optimizes the trade-off between storage density and program disturb susceptibility in each local region.
2Productivity
If more memory cells are programmed to increase storage density, then productivity is improved, but program disturb causes more fail bits reducing reliability
Solution Approach 1:
The memory array is segmented into different cell types within strings based on their position relative to selection lines. This segmentation enables selective programming strategies where cells are programmed in a sequence that minimizes program disturb, improving overall program operation reliability while maintaining high storage density.
Solution Approach 2:
The patent employs preliminary actions by programming memory cells in a specific sequence and using dummy memory cells as placeholders during the programming process. This preliminary arrangement of cells in the string reduces program disturb effects on actual data storage cells, thereby improving program operation reliability.
3Quantity of substance
If memory cells closer to drain selection line are used for storage, then storage capacity is improved, but they experience more program disturb leading to increased fail bits
Solution Approach 1:
Memory cells are differentiated by their position in the string: those closer to the source selection line store one bit and are less susceptible to program disturb, while those closer to the drain selection line store two bits and are positioned to tolerate the increased program disturb. This local quality differentiation optimizes the harmful effect distribution.
Solution Approach 2:
Dummy memory cells are introduced as placeholders or copies within the string structure. These dummy cells occupy positions that would otherwise be susceptible to program disturb, effectively copying the harmful effect away from actual data-storing memory cells and reducing fail bits in the functional cells.
Data Source
AI summary
A semiconductor memory device includes at least one cell string to include a plurality of dummy memory cells and a plurality of memory cells connected in series between the plurality of dummy memory cells; and the peripheral circuit to control the at least one cell string so that a first type of data represented by a first number of bits is stored in at least one of the dummy memory cells and a second type of data represented by a second number of bits, the second number smaller than the first number, is stored in at least two of the plurality of memory cells.