Memory Device Program Instruction Storage and Execution
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Solution Overview
Problem
Existing processing-in-memory (PIM) devices face challenges in efficiently providing a large number of program instructions to DRAM devices with minimal latency and interference, leading to increased power consumption and limited instruction bandwidth due to the need for larger and faster address/control buses, which complicates chip design and interferes with DRAM operations.
Innovation Solution
The solution involves a memory device with an array of memory cells and sensing circuitry that includes a sense amplifier and a compute component, coupled to a memory controller, allowing for the storage and execution of blocks of instructions within the memory array without transferring them via the address/control bus, enabling efficient execution of logical operations and reducing data movement and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If program instructions are transferred via address/control bus to DRAM devices, then instructions can be provided to processing resources, but data transfer latency increases and power consumption increases
Solution Approach 1:
The patent merges the storage of program instructions with the DRAM array itself, eliminating the need for separate instruction memory and transfer mechanisms. The DRAM array is configured to store both data and program instructions, with specific rows dedicated to instruction storage, thereby combining what were previously separate functions into a unified memory structure that reduces transfer latency and improves instruction bandwidth.
Solution Approach 2:
The patent implements preliminary action by pre-storing program instructions in the DRAM array before they are needed for execution. The instruction storage rows are filled with instructions in advance, allowing the processing resource to retrieve instructions without waiting for transfer from external memory, thus reducing latency and improving productivity.
2Productivity
If larger and faster address/control buses are used to provide more instructions, then instruction bandwidth increases, but chip design complexity increases and DRAM operations are interfered with
Solution Approach 1:
The patent segments the DRAM array into different functional rows: data storage rows and program instruction storage rows. This segmentation allows instructions to be stored within the existing memory structure without requiring separate instruction memory or complex address/control bus extensions, thereby increasing instruction bandwidth while avoiding increased chip design complexity.
Solution Approach 2:
The patent makes the DRAM array universal by enabling it to perform multiple functions: storing data, storing program instructions, and supporting processing operations. The same memory structure that traditionally served only data storage is now configured to also hold instructions, eliminating the need for separate instruction memory and complex bus architectures while maintaining DRAM operational efficiency.
3Ease of operation
If external processing resources are used to execute instructions, then processing functions can be performed, but power consumption increases and data transfer is required
Solution Approach 1:
The patent enables the DRAM array to serve itself by incorporating program instruction storage directly within the memory structure. The processing resource can execute instructions that are stored in the DRAM array without requiring continuous external data transfer or external processing intervention, thereby reducing power consumption while maintaining processing capability through self-contained memory-based operation.
Data Source
AI summary
The present disclosure includes apparatuses and methods related to a memory device as the store to program instructions. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller, coupled to the array and the sensing circuitry is configured to receive a block of instructions including a plurality of program instructions. The memory controller is configured to store the block of instructions in the array and retrieve program instructions to perform logical operations on the compute component.