Memory Device Program Loop Optimization via Dynamic Verification
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Solution Overview
Problem
Current memory devices face inefficiencies in program operation time due to unnecessary verify phases, which increase the overall time required for programming and reduce device performance.
Innovation Solution
A memory device and method that optimize program loops by starting verification for subsequent program states only after a pass in the previous state's verification phase, using an operation controller to manage program voltage and verify phases, and adjusting based on the number of memory cells and word line characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verification for all program states is performed sequentially in each program loop, then program operation completeness is ensured, but program operation time increases
Solution Approach 1:
The operation controller determines in advance which program states require verification in subsequent program loops based on the current verification results. By pre-planning the verification sequence and skipping already-verified states, the system performs necessary verification actions before time is lost, thereby reducing overall program operation time while maintaining completeness.
Solution Approach 2:
The verification process is made dynamic by adjusting the verification sequence based on real-time program operation results. The operation controller dynamically determines which program states to verify in each loop, skipping states that have already passed verification. This adaptive approach optimizes the balance between ensuring program completeness and minimizing operation time.
2Loss of time
If verification for subsequent program states is performed earlier, then program operation time is reduced, but verification accuracy may be compromised
Solution Approach 1:
The operation controller uses feedback from verification results to determine the next verification sequence. After each verification phase, the controller receives feedback on which program states have passed and which require further verification. This feedback mechanism ensures that verification accuracy is maintained by only skipping states that have definitively passed, while performing necessary verifications in an optimized sequence that reduces overall operation time.
3Productivity
If the number of verify phases is reduced, then device efficiency improves, but program state verification completeness may be affected
Solution Approach 1:
The operation controller extracts and removes redundant verification phases from the program operation sequence. By analyzing which program states have already passed verification and will not require further verification in subsequent loops, the controller eliminates unnecessary verify phases while maintaining verification completeness for all required states. This extraction of redundant operations improves device efficiency without compromising reliability.
Data Source
AI summary
Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, each having an erased state or any one of a plurality of program states, a peripheral circuit configured to perform a program operation including a plurality of program loops, and an operation controller configured to control the peripheral circuit so that, in response to a pass in verification for an N-th program state among the plurality of program states in a verify phase included in an x-th program loop among the plurality of program loops, verification for an N+M-th program state among the plurality of program states starts in a verify phase included in an x+1-th program loop among the plurality of program loops.