Memory Device Program Loops Voltage Increment Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory devices experience errors due to unintended changes in threshold voltages of memory cells, leading to data reliability issues, as these changes can occur due to various factors such as interference and environmental conditions.
Innovation Solution
An operation method for a memory device that involves performing multiple program loops with different program parameters, including varying program voltage increments, 2-step verify ranges, and bit line forcing voltages, to maintain threshold voltages within a narrow range, thereby minimizing performance reduction and enhancing data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple program loops with different program parameters are performed, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by varying program parameters (program voltage increment, 2-step verify range, bit line forcing voltage) across different program loops. Specifically, the program voltage increment is adjusted based on the program state being written, with different increment values applied for different threshold voltage ranges. This resolves the contradiction by improving data reliability through parameter optimization while managing complexity through systematic parameter variation rather than arbitrary complexity increases.
Solution Approach 2:
The patent implements dynamics by making the program operation adaptive and dynamic rather than static. The program parameters are dynamically adjusted based on the current program state and threshold voltage distribution. The system transitions from fixed parameter programs to dynamic parameter programs where the verify range and voltage increments are modified in real-time based on feedback from threshold voltage measurements, resolving the contradiction between reliability improvement and complexity management.
2Productivity
If program voltage increment is increased to improve programming speed, then productivity is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the programming process into multiple program loops, each targeting specific program states with different threshold voltage ranges. Instead of applying a single large voltage increment to all memory cells, the process segments the voltage application into controlled increments specific to each program state. This allows faster programming overall while maintaining precision for each segment, resolving the contradiction between productivity and manufacturing precision.
Solution Approach 2:
The patent implements local quality by applying different program voltage increments to different program states based on their specific requirements. Each program state receives a customized voltage increment tailored to its threshold voltage range and programming characteristics. This localized approach allows aggressive voltage increments for states that tolerate them while using conservative increments for states requiring precision, thereby achieving both high productivity and manufacturing precision simultaneously.
3Reliability
If 2-step verify range is widened to ensure complete programming verification, then reliability is improved, but loss of time increases
Solution Approach 1:
The patent applies partial or excessive action by performing verification at two different stages: an initial verify after the first program loop, and a final verify after the second program loop. The 2-step verify range is strategically designed to cover critical threshold voltage regions without unnecessarily extending to all possible ranges. This partial verification approach at key stages ensures reliability while minimizing total verification time compared to continuous or exhaustive verification methods.
Solution Approach 2:
The patent implements preliminary action by performing the first verify operation before completing all programming loops. This preliminary verification catches and corrects programming errors early in the process, preventing the need for extended final verification. By conducting verification in advance at intermediate stages, the system ensures reliability while reducing the overall time required for complete verification.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Disclosed is an operation method of a memory device that includes a plurality of memory cells stacked in a direction perpendicular to a substrate. The method includes performing first to (n-1)-th program loops on selected memory cells connected to a selected word line from among the plurality of memory cells, based on a first program parameter, and after the (n-1)-th program loop is performed, performing n-th to k-th program loops on the selected memory cells, based on a second program parameter different from the first program parameter. Herein, n is an integer greater than 1 and k is an integer greater than or equal to n. The first and second program parameters include information about at least two of a program voltage increment, a 2-step verify range, and a bit line forcing voltage used in the first to k-th program loops.