Semiconductor Memory Device Program Operation Voltage Control
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Solution Overview
Problem
Current NAND flash memory devices face inefficiencies in write operations due to the high number of verification reads required, which increases the total time for writing data, especially as the number of write states increases, and struggles to effectively manage the variation in threshold voltage between memory cell transistors.
Innovation Solution
The semiconductor memory device employs a method involving multiple program loops with classification reads to categorize memory cell transistors into low and high threshold voltage groups, adjusting the program voltage and verify voltage accordingly, reducing the width of the threshold voltage distribution lobes and thereby reducing the number of verification reads and total write operation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple verification reads are performed to ensure accurate data writing in NAND flash memory, then the reliability of data storage is improved, but the write operation time increases significantly
Solution Approach 1:
The patent segments memory cell transistors into multiple groups based on their threshold voltage characteristics. By performing classification reads on different groups sequentially and applying different program voltages to different groups, the system reduces the total number of verification reads needed while maintaining data reliability. This segmentation allows parallel processing of different memory groups with optimized verification strategies for each group.
Solution Approach 2:
The patent dynamically changes the program voltage parameter applied to memory cell transistors based on their threshold voltage characteristics. By adjusting the program voltage according to the specific group being programmed (determined through classification reads), the system achieves accurate data writing with fewer verification reads, thus reducing write operation time while maintaining reliability.
2Quantity of substance
If the number of write states is increased to enhance storage capacity, then the amount of data that can be stored is improved, but the number of verification reads required increases
Solution Approach 1:
The patent divides memory cell transistors into multiple groups based on their threshold voltage distributions, which becomes increasingly important as the number of write states increases. By segmenting the memory and applying group-specific program voltages determined through classification reads, the system manages the complexity of multiple write states without proportionally increasing verification read requirements.
Solution Approach 2:
The patent employs dynamic adjustment of program voltage parameters tailored to each memory group's threshold voltage characteristics. This parameter optimization allows the system to handle multiple write states efficiently, reducing the verification overhead that would otherwise scale linearly with the number of write states.
3Device complexity
If uniform program voltage is applied to all memory cell transistors, then the device complexity is reduced, but the variation in threshold voltage cannot be effectively managed
Solution Approach 1:
The patent segments memory cell transistors into multiple groups based on their threshold voltage characteristics and applies different program voltages to different groups. This segmentation strategy manages threshold voltage variation effectively while adding only moderate complexity to the voltage control system, as the grouping and voltage assignment can be automated through classification reads.
Solution Approach 2:
The patent applies the principle of local quality by tailoring the program voltage to the specific characteristics of each memory group. Instead of using a uniform voltage, each group receives a customized program voltage that matches its threshold voltage distribution, thereby achieving precise threshold voltage control while managing the added complexity through systematic group-based management.
Data Source
AI summary
A semiconductor memory device comprises a first word line coupled to first and second memory cell transistors, first and second bit lines, and a controller. In a first program loop, a controller applies a first voltage to first and second bit lines in a program operation, and classifies the first and second memory cell transistors into first and second groups by applying a first verify voltage to the first word line in a verify operation. In a program operation of each of program loops that are executed after the first program loop, the controller applies the first voltage to the first bit line when a verification of the first memory cell transistor has not been passed, and applies a second voltage to the second bit line when a verification of the second memory cell transistor has not been passed.