Memory Device Quick Pass Write Programming via Sense Node Discharge
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Solution Overview
Problem
Existing memory device programming techniques face inefficiencies in determining if memory cells are within Quick Pass Write (QPW) windows, leading to suboptimal programming speed and reliability due to the need for multiple verify pulses and potential over-programming issues.
Innovation Solution
A method and system for programming memory devices that utilize dual zone QPW programming by applying different biasing voltages based on threshold voltage determinations, using a single verify pulse to assess the QPW zones, and adjusting programming pulses accordingly to maintain optimal voltage gaps between verify low and high voltages, thereby improving reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple verify pulses are used to determine QPW zones, then measurement precision of threshold voltage is improved, but verify time increases
Solution Approach 1:
The patent combines multiple verify operations into a single verify pulse by charging a sense node to a voltage between VL1 and VH and discharging it through the memory cell channel. This single discharge operation simultaneously provides information about whether the threshold voltage is below VL1, between VL1-VL2, between VL2-VH, or above VH, eliminating the need for multiple separate verify pulses while maintaining measurement precision
Solution Approach 2:
The sense node acts as an intermediary element that enables simultaneous verification of multiple threshold voltage zones. By charging the sense node to an intermediate voltage and measuring discharge time through the memory cell, the system can determine the QPW zone without directly applying multiple verify pulses to the memory cell, thus reducing verify time while maintaining precision
2Reliability
If dual zone QPW programming is implemented, then programming reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements dual zone QPW programming by dynamically changing the bit line voltage parameter based on the determined threshold voltage zone. When the threshold voltage is between VL1 and VH, a first QPW voltage is applied; when between VL2 and VH, a second QPW voltage is applied. This parameter change approach maintains programming reliability while using simple voltage selection logic rather than complex control mechanisms
Solution Approach 2:
The patent applies different QPW voltages to different memory cells based on their individual threshold voltage characteristics. By determining each cell's zone through the sense node discharge method and applying appropriate QPW voltages selectively, the system achieves reliable programming with localized control rather than global complexity
3Manufacturing precision
If QPW voltage is applied to slow programming, then manufacturing precision of threshold voltage distribution is improved, but programming speed decreases
Solution Approach 1:
The patent dynamically adjusts the QPW voltage applied to bit lines based on real-time determination of memory cell threshold voltage zones. By using the sense node discharge time to identify whether cells are in the first or second QPW zone, the system applies appropriate QPW voltages only when needed and only to specific cells, maintaining precision while minimizing the impact on overall programming speed through selective and adaptive control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces verify time, enhances programming reliability by tightening threshold voltage distributions, and maintains performance without the penalties associated with dual zone QPW programming, achieving a 9.2% performance gain or 252 mV VT margin improvement.
Implementation Method 1
discharging a sense node through a channel including the at least one memory cell and comparing a discharge time to predetermined sense times associated with the first and second verify low voltages and with the verify high voltage
Implementation Method 2
The memory cells of a selected word line are programmed to respective data states by applying a series of programming pulses to a control gate of the selected word line in a plurality of program-verify iterations to thereby trap electrons in charge-trapping materials of the memory cells
Data Source
AI summary
The memory device includes a controller that is configured to program the memory cells of a selected word line in a plurality of program-verify iterations. During a verify portion at least one of the program-verify iterations, the controller determines a threshold voltage of at least one memory cell relative to a first verify low voltage VL1, a second verify low voltage VL2, and a verify high voltage VH associated with a data state being programmed. The controller also maintains a count of program-verify iterations since the at least one memory cell passed a verify high voltage of a previously programmed data state or discharges a sense node through a channel including the at least one memory cell and compares a discharge time to predetermined sense times associated with the first and second verify low voltages and with the verify high voltage.