Memory Device Queue Layer Double Data Rate Command Processing
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Solution Overview
Problem
Conventional storage devices face performance limitations due to fixed input speeds of commands and addresses, which hinder the improvement of data processing efficiency as the speed difference between data input and command/address input becomes significant.
Innovation Solution
Incorporating a queue layer in the memory device that temporarily stores and processes commands and addresses based on the rising and falling edges of a write enable signal, allowing for high-speed input and processing of commands and addresses, potentially at a double data rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional fixed input speed for commands and addresses is used, then device complexity is reduced, but productivity deteriorates due to speed mismatch between data input and command/address input
Solution Approach 1:
The input circuit is segmented into separate paths: a first input circuit for commands and addresses using a first clock signal, and a second input circuit for data using a second clock signal. This segmentation allows each path to operate at optimized speeds independently, resolving the contradiction between productivity improvement and device complexity.
Solution Approach 2:
The patent introduces dynamic clock signaling where the first clock signal for commands and addresses can operate at a different frequency than the second clock signal for data. This dynamic approach allows the system to adapt input speeds to match processing capabilities, improving productivity without requiring overly complex fixed-speed circuits.
2Productivity
If high-speed data input is implemented, then productivity improves, but reliability deteriorates due to command/address input speed limitations
Solution Approach 1:
By separating the input circuits into distinct pathways with independent clock signals, the patent ensures that high-speed data input does not interfere with command and address processing. The first input circuit maintains reliable command processing at its optimized speed while the second input circuit achieves high-speed data input, thus resolving the reliability-productivity contradiction.
3Productivity
If queue layer is added to temporarily store commands and addresses, then productivity improves through double data rate processing, but device complexity increases
Solution Approach 1:
The queue layer utilizes dynamic clock signaling to achieve double data rate processing. By employing a first clock signal specifically for the queue layer that can operate at twice the frequency of the main data clock, the system achieves higher command processing speeds without requiring a completely redesigned input circuit structure, thus balancing productivity improvement with acceptable device complexity.
Data Source
AI summary
Provided herein is a memory device and a storage device including the same. The memory device includes an input/output circuit configured to receive a command, an address, and data from a memory controller. The memory device also includes control logic configured to control a peripheral circuit of the memory device so that an operation of storing the data in a memory cell of the memory device is performed based on the command and the address received from the input/output circuit. The input/output circuit includes a queue layer configured to temporarily store the command and the address and to output the command and the address to the control logic based on at least one of a rising edge and a falling edge of a write enable signal received by the memory device from the memory controller.