Memory Device Queuing Controller Commands for Parallel Execution
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Solution Overview
Problem
Current memory systems face inefficiencies in random read and program operations due to sequential execution of commands, which can lead to performance bottlenecks and increased latency.
Innovation Solution
A memory system architecture that includes multiple memory devices with device queues and a queue command execution control circuit, allowing for parallel execution of commands across multiple channels and interleaving operations to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If commands are executed sequentially in traditional memory systems, then the system structure remains simple, but the random read and program performance deteriorates due to performance bottlenecks and increased latency
Solution Approach 1:
The memory system is segmented into multiple independent memory devices (first memory device, second memory device, etc.) that can operate in parallel. Each memory device has its own command queue and execution control circuit, allowing simultaneous processing of multiple commands across different devices, thereby improving random read and program performance without creating a single point of bottleneck.
Solution Approach 2:
The system transitions from single-channel sequential execution to multi-channel parallel execution by adding the dimension of multiple memory devices and command queues. This dimensional expansion allows commands to be executed simultaneously across different channels, fundamentally changing the execution model from sequential to parallel and resolving the performance bottleneck.
2Productivity
If multiple commands are queued and executed in parallel across multiple memory devices, then random read and program performance improves, but the device complexity increases due to additional queues and control circuits
Solution Approach 1:
The execution control function is extracted from a centralized controller and distributed to individual memory devices. Each memory device contains its own queue command execution control circuit that independently manages its command queue, eliminating the need for complex centralized arbitration and control logic while enabling parallel execution.
Solution Approach 2:
Each memory device is self-sufficient with its own command queue and execution control circuit, allowing it to autonomously manage and execute commands without requiring constant intervention from a central controller. This self-service approach simplifies the overall control architecture while maintaining high parallel execution capability.
3Loss of time
If commands are processed sequentially through a single channel, then the control logic remains simple, but latency increases due to waiting for previous commands to complete
Solution Approach 1:
Multiple commands are pre-loaded into the device queue before execution begins. The queue command execution control circuit is designed to efficiently process multiple queued commands in parallel across different memory devices, reducing the time commands spend waiting in line and minimizing overall execution latency.
Data Source
AI summary
A memory system includes a plurality of memory devices configuring a plurality of ways, and a memory controller communicating with the plurality of memory devices through a channel, wherein each of the plurality of memory devices includes a device queue, and wherein the device queue queues a plurality of controller commands inputted from the memory controller.