Memory Device Queuing for Parallel Command Execution
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Solution Overview
Problem
Current memory systems face inefficiencies in random read and program performance due to sequential execution of commands, which limits parallel processing and overall system performance.
Innovation Solution
A memory system with multiple memory devices and a memory controller that utilizes command queues to queue and execute commands in parallel, allowing for simultaneous execution of multiple commands across different memory devices, thereby enhancing performance through full-way interleaving.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If commands are executed sequentially in conventional memory systems, then the system structure remains simple, but random read and program performance deteriorates
Solution Approach 1:
The memory system is segmented into multiple independent memory devices (Way0, Way1, Way2, Way3) that can operate in parallel. Each memory device has its own command queue and execution control circuit, allowing simultaneous processing of multiple commands across different devices, thereby improving random read and program performance without requiring a fundamentally complex system architecture
Solution Approach 2:
The patent introduces a new dimension of parallelism by implementing full-way interleaving across multiple memory devices. Instead of sequential execution in a single dimension, commands are distributed across multiple ways (devices) and executed simultaneously, effectively adding spatial parallelism to the system
2Productivity
If multiple commands are queued and executed in parallel across multiple memory devices, then command execution efficiency improves, but device complexity increases
Solution Approach 1:
Each memory device is equipped with its own command queue and queue command execution control circuit, enabling self-service operation. The control circuit automatically manages command execution without requiring centralized control, reducing the complexity of the overall system while improving execution efficiency through parallel autonomous operation
Solution Approach 2:
Commands are pre-queued in the device queue before execution. The queue command execution control circuit retrieves commands from the queue and executes them in parallel across multiple memory devices, preparing the execution pipeline in advance to maximize throughput and efficiency
Data Source
AI summary
A memory system includes a plurality of memory devices configuring a plurality of ways, and a memory controller communicating with the plurality of memory devices through a channel, wherein each of the plurality of memory devices includes a device queue, and wherein the device queue queues a plurality of controller commands inputted from the memory controller.