Memory Device Redundant Word Line Repair Allocation
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Solution Overview
Problem
Existing memory device repair schemes for defective word lines are inefficient, leading to high redundant word line utilization and hardware costs due to fixed allocation of repair regions across different stages.
Innovation Solution
A memory device design where all redundant word line sets are available for repairs across multiple stages, with flexible allocation during the wafer, package, and post-package stages, allowing for increased utilization and cost-effective hardware usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant word lines are divided into three non-overlapping regions allocated to different stages, then each stage has dedicated repair resources, but the utilization rate of redundant word lines becomes low and hardware costs increase
Solution Approach 1:
The patent makes all M redundant word line sets available for repair operations across all three stages (wafer, package, and post-package stages) rather than allocating specific RWL sets to specific stages. This multi-functional approach allows any RWL set to repair defective WL sets at any stage, significantly improving utilization rate while maintaining reliable repair capability throughout the manufacturing process
2Reliability
If redundant word lines are divided into three non-overlapping regions allocated to different stages, then each stage has dedicated repair resources, but hardware costs increase
Solution Approach 1:
By making all M RWL sets universally available across all stages, the patent eliminates the need for separate dedicated RWL regions for each stage. The memory control circuit manages repair operations flexibly, selecting from all available RWL sets regardless of stage, thereby reducing hardware complexity and costs while maintaining comprehensive repair capability
Solution Approach 2:
The patent merges the repair resources of all three stages into a single pool of M RWL sets that can be used by any stage. Instead of having separate RWL regions for wafer, package, and post-package stages, all stages share the same RWL resources, reducing overall hardware requirements and costs
3Productivity
If all redundant word line sets are available for repairs across multiple stages, then utilization rate increases and hardware costs decrease, but repair management complexity increases
Solution Approach 1:
The memory control circuit implements feedback mechanisms to track the status and availability of RWL sets across different stages. By monitoring which RWL sets are currently being used or available, the control circuit can dynamically allocate resources, manage repairs efficiently, and maintain optimal utilization without excessive complexity
Data Source
AI summary
The disclosure provides a memory device which includes a plurality of word lines grouped into a plurality of WL sets; and a plurality of redundant word lines grouped into M RWL sets; and a memory control circuit connected to the WL sets and the RWL sets and configured to replace a plurality of defective WL sets of the plurality WL sets by selecting from the RWL sets, wherein each of the plurality of defective WL sets comprises at least a defective word line, all of the M RWL sets are available for repairing the WL sets during a wafer stage, where M is an integer greater than 2, and N of M RWL sets is available for repairing the WL sets during the wafer stage, during a package stage and during a post package stage, where N is an integer less than M.