Memory Device Intermittent Failure Detection and Refresh Control
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Solution Overview
Problem
Memory devices face intermittent failures due to degradation of initial electrical charge in cell capacitors, which are difficult to detect and correct, especially as integration increases and capacitance reduces, leading to sporadic 1-bit failures and inefficiencies in refresh operations.
Innovation Solution
A memory device with a refresh counter, address storage circuit, error detection unit, and refresh control unit that detects and corrects intermittent failures by generating refresh addresses, storing additional refresh addresses, and controlling the refreshing of memory cells based on specific conditions to delay and optimize the refresh process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration of memory devices increases and the width of line patterns decreases, then the capacitance of the cell capacitor is reduced, but the voltage difference for distinguishing data becomes smaller making detection more difficult
Solution Approach 1:
The patent applies preliminary action by performing a detection operation before the refresh operation. The detection period is set to occur before the refresh period, allowing the system to identify failed memory cells in advance and apply corrective measures during the subsequent refresh phase, thereby preventing data loss despite reduced voltage margins
Solution Approach 2:
The patent introduces an intermediary detection mechanism that mediates between the storage function and the refresh function. The detection operation acts as an intermediary step that identifies failed cells without directly interfering with the normal refresh operation, enabling separate detection and correction phases
2Productivity
If a typical refresh operation is performed on a constant cycle, then memory cells are refreshed regularly, but intermittent failures occurring during time intervals between refresh operations remain undetected and uncorrected
Solution Approach 1:
The patent merges the detection operation and refresh operation into a unified two-phase refresh structure. The detection period and refresh period are combined in sequence, allowing the system to both identify failed cells and correct them within a single refresh cycle, thereby improving reliability without sacrificing refresh efficiency
Solution Approach 2:
The patent ensures continuity of useful action by making the detection operation occur continuously during the detection period, which is integrated into the refresh cycle. This continuous detection capability ensures that intermittent failures are caught as soon as they occur, maintaining ongoing protection against data loss
3Duration of action of stationary object
If memory cells are refreshed sequentially according to refresh addresses, then all memory cells are eventually refreshed, but failed memory cells cannot be identified and corrected among them
Solution Approach 1:
The patent applies segmentation by dividing the refresh operation into two distinct segments: a detection period for identifying failed cells and a refresh period for correcting them. This segmentation allows the system to separately handle detection and correction tasks, making failed cell identification possible without disrupting the overall refresh process
Data Source
AI summary
A memory device may include a plurality of memory cells; a refresh counter suitable for generating a refresh address; an address storage circuit suitable for storing an additional refresh address; an error detection unit suitable for detecting an error of selected memory cells of the plurality of memory cells in response to a refresh command in a detection period; and a refresh control unit suitable for refreshing memory cells corresponding to the refresh address or the additional refresh address among the memory cells in response to the refresh command, and controlling the refreshing of the memory cells to be delayed in the detection period.