Semiconductor Memory Device Self Refresh Current Reduction
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Solution Overview
Problem
Conventional semiconductor memory devices with hierarchical bit line structures and single-ended sense amplifiers face challenges in reducing consumption current and maintaining sensing margin during self refresh mode due to parasitic capacitance and leak current effects, especially for high-level data storage.
Innovation Solution
A semiconductor memory device with a hierarchical bit line structure and single-ended sense amplifier that controls the connection between amplifying elements and signal voltage decision units at different timings in normal and refresh operations, prolonging the determination time for signal voltage in self refresh mode to reduce consumption current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a hierarchical bit line structure is employed to reduce parasitic capacitance and resistance, then the sensing performance is improved, but the circuit scale increases and consumption current rises
Solution Approach 1:
The bit line structure is segmented into local bit lines and global bit lines, where local bit lines connect to sense amplifiers and global bit lines connect to external terminals. This segmentation reduces the number of memory cells per local bit line, enabling the use of simpler single-ended sense amplifiers while maintaining overall sensing performance.
2Use of energy by moving object
If the refresh interval is extended to reduce consumption current in self refresh mode, then energy efficiency is improved, but the sensing margin decreases due to leak current
Solution Approach 1:
The sense amplifier operates in different states depending on the mode: in normal operation mode, the determination circuit is connected to the bit line for rapid data readout; in self refresh mode, the determination circuit is disconnected and the bit line is maintained in a high-impedance state, allowing extended refresh intervals while maintaining sensing margin.
3Device complexity
If a single-ended sense amplifier is used instead of a differential sense amplifier, then circuit scale is reduced, but the ability to handle high-level data in self refresh mode deteriorates
Solution Approach 1:
The determination circuit is extracted as a separate functional block from the sense amplifier. In self refresh mode, this determination circuit is disconnected from the bit line, allowing the single-ended sense amplifier to maintain high-level data without the need for differential operation, thus preserving both circuit simplicity and sensing margin.
Data Source
AI summary
A semiconductor memory device comprises a memory cell array, first and second bit lines, first and second amplifiers, and a sense amplifier control circuit. An amplifying element in the first sense amplifier amplifiers the signal of the first bit line and converts it into an output current. The second bit line is selectively connected to the first bit line via the first sense amplifier. A signal voltage decision unit in the second sense amplifier determines the signal level of the second bit line being supplied with the output current. The sense amplifier control circuit controls connection between the amplifying element and the unit in accordance with a determination timing, which switches the above connection from a connected state to a disconnected state at a first timing in a normal operation and switches in the same manner at a delayed second timing in a refresh operation.