Memory Device Row-Column Command Segmentation for Lower Latency
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Solution Overview
Problem
Existing memory devices face challenges in efficiently managing high-capacity and high-bandwidth data processing, particularly in electronic devices like smartphones and AI accelerators, due to the need for an efficient input and output interface method between host devices and memory controllers.
Innovation Solution
A memory device design that includes separate row and column pins for receiving commands, with specific timing protocols for active, read/write, and precharge commands, allowing for parallel processing and reduced command latency through differential clock signal usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single interface method is used for command input, then the interface structure is simple, but the command processing speed and efficiency are limited
Solution Approach 1:
The command input interface is segmented into two separate pin groups: row pins for receiving row commands (active command, precharge command) and column pins for receiving column commands (read command, write command). This segmentation allows independent parallel processing of different command types, improving command processing speed while maintaining a relatively simple overall interface structure.
2Productivity
If commands are processed sequentially through a single interface, then the interface design is straightforward, but the throughput and bandwidth are reduced
Solution Approach 1:
The command input interface is segmented into two separate pin groups: row pins for receiving row commands (active command, precharge command) and column pins for receiving column commands (read command, write command). This segmentation allows independent parallel processing of different command types, improving command processing speed while maintaining a relatively simple overall interface structure.
3Loss of time
If traditional command timing protocols are used, then the timing control is simple, but the latency in continuous memory access operations is high
Solution Approach 1:
The command input interface is segmented into two separate pin groups: row pins for receiving row commands (active command, precharge command) and column pins for receiving column commands (read command, write command). This segmentation allows independent parallel processing of different command types, improving command processing speed while maintaining a relatively simple overall interface structure.
Solution Approach 2:
The timing protocol uses periodic clock signals (CK0, CK1) with specific rising and falling edges to trigger command reception at defined intervals. This periodic structure enables predictable timing and reduced latency in continuous memory access operations while keeping the timing control logic manageable.
Data Source
AI summary
A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.