Memory Device Row Hammer Mitigation via Randomized Refresh

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Solution Overview

Problem

As the degree of integration of memory devices increases, the coupling effect between adjacent word lines increases, leading to the row hammer phenomenon, where data of memory cells connected to a word line adjacent to an often activated word line becomes corrupted.

Innovation Solution

A memory device and system that includes a memory cell array, a first random number generator to generate a pseudo random bit sequence, and memory cell row picking circuits to randomly select memory cell rows and store their addresses in queues, with a refresh control circuit performing refresh operations on adjacent memory cell rows.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the degree of integration of memory devices increases, then the memory capacity and density are improved, but the coupling effect between adjacent word lines increases leading to row hammer phenomenon

Engineering Contradiction:
Improvememory capacityVSAvoidcoupling effect between word lines
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent performs preliminary identification of memory cell rows that are likely to be affected by row hammer attacks before actual corruption occurs. By monitoring access patterns and identifying frequently accessed rows, the system proactively prepares refresh operations for adjacent rows that are vulnerable to coupling effects, preventing data corruption before it happens.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the memory cell array into multiple groups based on their vulnerability to row hammer attacks. By dividing the memory into different regions with different refresh strategies, the system can apply targeted refresh operations only to vulnerable segments rather than refreshing the entire memory array, thus mitigating the coupling effect in high-risk areas while maintaining efficient operation in low-risk areas.

Inventive Principle:
Principle #1Segmentation

2Reliability

If random refresh operations are performed on memory cell rows to mitigate row hammer phenomenon, then data reliability is improved, but the complexity of the refresh control circuit increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidrefresh control circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the refresh control circuit continuously monitors access patterns to memory cell rows and uses this information to dynamically adjust refresh operations. The circuit receives feedback about which rows are frequently accessed and automatically identifies adjacent rows that need refresh, creating a closed-loop system that adapts to actual usage patterns rather than following a fixed complex schedule.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The refresh control circuit performs self-service by autonomously identifying vulnerable memory rows and generating appropriate refresh commands without requiring external intervention or complex pre-programmed schedules. The circuit uses its own monitoring capabilities to detect access patterns and automatically determines which rows need refresh, simplifying the overall control architecture while maintaining high data reliability.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20250103217A1Memory device, memory system, and operating method of memory device
Publication Date: 2025.03.27 SAMSUNG ELECTRONICS CO LTD
  • US20250103217A1 patent drawing
  • US20250103217A1 patent drawing
  • US20250103217A1 patent drawing

AI summary

A memory device includes a memory cell array including memory cell rows, a first random number generator generating an n-bit first pseudo random bit sequence signal based on a first seed and a first degree, first and second memory cell row picking circuits, and a refresh control circuit. The first memory cell row picking circuit randomly selects a first memory cell row at a first cycle, and stores a row address of the selected first memory cell row in a first queue. The second memory cell row picking circuit randomly selects a second memory cell row at a second cycle, and stores a row address of the selected second memory cell row in a second queue. The refresh control circuit performs a refresh operation on memory cell rows physically adjacent to memory cell rows corresponding to each of the row addresses stored in the first queue and the second queue.