Semiconductor Memory Device Row Hammering Defense

The memory device is divided into multiple cell mats (first cell mat and second cell mat), each with its own row-hammer cells that independently track access counts. This segmentation allows the system to manage refresh operations for each cell mat separately, reducing the complexity of determining which rows need refreshing while maintaining comprehensive row hammering protection across all repaired columns.

Row-hammer cells are integrated into each row structure to autonomously count the number of times that row and its paired row are activated. When the access count reaches a threshold, the system automatically triggers a target refresh operation on that specific row and its adjacent rows. This self-monitoring mechanism ensures data protection is applied only where and when needed, minimizing unnecessary power consumption while maintaining robust protection against row hammering attacks.

Each row-hammer cell serves multiple functions: it counts activations for its associated row, indirectly monitors its paired row through the 2WL column repair relationship, and triggers refresh operations when thresholds are exceeded. This multi-functional design allows accurate tracking of access patterns across both cell mats without requiring separate counting mechanisms for each row, thereby reducing the overall number of row-hammer cells needed while maintaining high accuracy in refresh operation selection.