Semiconductor Memory Device Runtime Error Repair
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Solution Overview
Problem
Semiconductor memory devices, particularly DRAMs, face increasing error bits and decreased yield due to shrinking fabrication design rules, leading to operational issues after being mounted in SSDs, as existing repair schemes are ineffective for faults occurring post-manufacturing.
Innovation Solution
A semiconductor memory device and system that includes a memory cell array, an error correction code (ECC) engine, an I/O gating circuit, an error information register, and a control logic circuit, which performs ECC decoding, accumulates error information, and executes runtime repair operations to correct errors detected during operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rules are shrunk to increase memory capacity, then storage density is improved, but error bit rate increases and yield decreases
Solution Approach 1:
The patent performs preliminary error detection and accumulation during refresh operations before the memory device is fully operational. The ECC engine continuously monitors and records error locations in an error information register during periodic refresh cycles, enabling proactive identification of defective cells before they cause operational failures.
Solution Approach 2:
The memory device performs self-diagnosis and self-repair by using its own refresh operations to detect errors and automatically mapping defective addresses to replacement addresses. The device monitors its own error patterns and executes repair operations without external intervention, enhancing reliability while maintaining high capacity.
2Productivity
If traditional repair schemes are used during manufacturing, then yield is improved, but runtime error correction capability is insufficient
Solution Approach 1:
The patent implements a feedback mechanism where error information is continuously accumulated during runtime operations and used to dynamically adjust the address mapping. The error information register feeds back defect locations to the control logic, which updates replacement address mappings in real-time, enabling continuous improvement of reliability during the device's operational life.
Solution Approach 2:
The repair mechanism transitions from static manufacturing-time repair to dynamic runtime repair. The address mapping is not fixed but dynamically updated based on continuously monitored error patterns, allowing the system to adapt to newly emerging defects and provide ongoing error correction capability throughout the device's lifespan.
3Reliability
If ECC decoding is performed on all data reads, then error detection capability is improved, but operation speed decreases
Solution Approach 1:
Instead of performing full ECC decoding on every data read operation, the patent applies ECC decoding selectively during refresh operations and only when specifically requested. The partial approach of monitoring errors during routine refresh cycles provides sufficient error detection capability without the performance penalty of continuous decoding on all data accesses.
Solution Approach 2:
The patent uses periodic refresh operations as the primary mechanism for error detection, leveraging the existing periodic nature of DRAM refresh requirements. By performing ECC decoding during these mandatory periodic refresh cycles rather than on every data access, the system maintains high error detection capability while preserving fast read/write speeds for normal operations.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit connected between the memory cell array and the ECC engine, an error information register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The control logic circuit controls the ECC engine, the I/O gating circuit and the error information register based on a command and address. The I/O gating circuit provides the ECC engine with codewords which are read from the memory cell array through refresh operations on the plurality of memory cell rows. The ECC engine performs an ECC decoding on main data of the codewords based on parity bits of the codewords and provides error generation signals to the control logic circuit in response to detecting correctable errors with respect to a corresponding address resulting from performing the ECC decoding.