Semiconductor Memory Device Second Conductive Layer Voltage Drop

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Solution Overview

Problem

In semiconductor memory devices, the high electrical resistance of the P-type impurity layer leads to significant voltage drops during write and erase operations, complicating the manufacturing process and reducing efficiency, especially when N-type impurity implantation is required to minimize interface resistance.

Innovation Solution

Incorporating a second conductive layer made of low resistivity material, such as metal, between the P-type impurity layer and the first conductive layer, allowing electrons and holes to flow more efficiently, thereby reducing voltage drops and eliminating the need for N-type impurity implantation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a P-type impurity layer is used in the memory device, then the manufacturing process is simplified, but the electrical resistance increases causing significant voltage drops during write and erase operations

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidelectrical performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A second conductive layer made of low-resistivity material (such as metal) is introduced between the P-type impurity layer and the first conductive layer. This intermediary layer serves as a mediator that provides a low-resistivity path for current flow, thereby reducing voltage drops during write and erase operations while maintaining the manufacturing simplicity of using a P-type impurity layer.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If N-type impurity implantation is performed to reduce interface resistance, then the electrical resistance decreases, but the manufacturing process becomes more complex

Engineering Contradiction:
Improveinterface resistanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The second conductive layer acts as an intermediary that eliminates the need for N-type impurity implantation. By providing a low-resistivity metal path between the P-type impurity layer and the first conductive layer, it achieves the same electrical performance benefit without requiring the additional complex implantation process.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If the P-type impurity layer is used without additional conductive layers, then the device structure is simpler, but voltage drops during write and erase operations increase

Engineering Contradiction:
Improvestructural complexityVSAvoidvoltage drop
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The second conductive layer is introduced as a thin intermediary layer that adds minimal structural complexity while significantly reducing voltage drops. The low-resistivity material provides an efficient current path that reduces energy loss during write and erase operations without substantially increasing device complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the efficiency of write and erase operations by reducing voltage drops and simplifying the manufacturing process, as the second conductive layer acts as a low-resistivity path for electrons and holes, improving overall device performance.

Implementation Method 1

Incorporating a second conductive layer made of low resistivity material, such as metal, between the P-type impurity layer and the first conductive layer, allowing electrons and holes to flow more efficiently

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS9978770B2Semiconductor memory device
Publication Date: 2018.05.22 KIOXIA CORP
  • US9978770B2 patent drawing
  • US9978770B2 patent drawing
  • US9978770B2 patent drawing

AI summary

According to an embodiment, a semiconductor memory device comprises a substrate, a plurality of first conductive layers, a memory columnar body, a first semiconductor layer, a second semiconductor layer and a contact. The plurality of first conductive layers are stacked upwardly of the substrate. The memory columnar body extends in a first direction intersecting an upper surface of the substrate and a side surface of the memory columnar body is covered by the first conductive layers. The first semiconductor layer is connected to a lower end of the memory columnar body and extends in a second direction intersecting the first direction. The second conductive layer is provided between the first semiconductor layer and the first conductive layers. The second conductive layer is connected to the memory columnar body and extending in the second direction. The contact is connected to the second conductive layer and extends in the first direction.