Memory Device Segmentation for Data Reliability
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Solution Overview
Problem
In neuromorphic computer systems and autonomous driving apparatuses, existing memory devices lack efficient data storage methods that consider the importance of data, leading to degraded reliability and operational efficiency due to uniform data programming across memory cells.
Innovation Solution
A memory device with a single semiconductor chip featuring a first memory area for storing N-bit data and a second memory area for storing M-bit data, where M > N, allowing data to be stored based on importance, with shared input and output interfaces and a controller that applies weights to sensing data for optimal storage in either area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored uniformly in all memory cells without considering importance, then the memory device structure remains simple, but reliability and operational efficiency degrade
Solution Approach 1:
The memory device is divided into multiple memory areas (first memory area for N-bit data, second memory area for M-bit data where M>N) with different reliability characteristics. This segmentation allows critical data to be stored in higher reliability areas while less critical data goes to lower reliability areas, thereby improving overall system reliability without requiring a complete redesign of the memory structure.
Solution Approach 2:
Different memory areas are assigned different data storage capabilities (N-bit vs M-bit) and reliability levels based on their local characteristics. The first memory area uses a first peripheral circuit for N-bit data access, while the second memory area uses a second peripheral circuit for M-bit data access. This local differentiation enables optimized data storage according to importance without uniform complexity across the entire device.
2Reliability
If critical data is stored in higher reliability areas, then data reliability improves, but storage capacity for less critical data decreases
Solution Approach 1:
The memory device adds a dimension of data importance classification by organizing memory areas not just by capacity but by reliability levels. The first memory area (N-bit) provides higher reliability for critical data, while the second memory area (M-bit, where M>N) provides lower reliability but higher capacity for less critical data. This dimensional organization allows simultaneous optimization for both reliability and total storage capacity.
Data Source
AI summary
A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data according to an M-bit data access scheme, where N is a natural number, and a first peripheral circuit for controlling the first memory cells and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data according to an M-bit data access scheme, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells and disposed below the second memory cell array, the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight.