Semiconductor Memory Device With Segmented Drain Select Lines
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Solution Overview
Problem
Semiconductor memory devices face challenges in efficiently managing multiple cell strings with shared drain select lines, leading to increased area requirements and complex manufacturing processes.
Innovation Solution
A semiconductor memory device design that includes a memory cell array with multiple memory blocks sharing a common source line and one or more drain select lines, along with a peripheral circuit and control logic to program connection control and drain select transistors, allowing for selective operation and coding of memory blocks to reduce area and simplify manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple cell strings share a drain select line, then the area of the memory cell array is reduced, but the complexity of controlling selective operation increases
Solution Approach 1:
The drain select line is divided into multiple segments, each corresponding to a specific memory block. By segmenting the shared drain select line, the patent enables selective activation of specific memory blocks while sharing the physical line structure, thus reducing area while maintaining controllability.
Solution Approach 2:
Connection control transistors are programmed in advance to establish predetermined conductive states that enable or disable access to specific memory blocks. This preliminary programming allows the control logic to selectively operate on target memory blocks without complex real-time control mechanisms.
2Ease of operation
If drain select lines are separated for each memory block, then selective operation is simplified, but the area of the memory cell array increases
Solution Approach 1:
Multiple drain select lines are merged into a single shared physical line structure. The patent combines the functionality of multiple separate drain select lines into one shared line that can be selectively activated for different memory blocks through the use of connection control transistors and coding-programmed drain select transistors.
Solution Approach 2:
The shared drain select line serves multiple functions by being capable of selecting different memory blocks through programmable transistors. This universal line structure replaces multiple dedicated lines, reducing area while maintaining the ability to perform selective operations on any memory block.
3Ease of manufacture
If coding-programming is applied to drain select transistors, then manufacturing process is simplified, but the programming complexity increases
Solution Approach 1:
The drain select transistors are coding-programmed to automatically establish their conductive states based on predetermined codes. This self-programming capability eliminates the need for complex external programming mechanisms, simplifying the manufacturing process while the programming is performed once during fabrication.
Data Source
AI summary
Disclosed are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes: a memory cell array including a plurality of memory blocks sharing one or more drain select lines; a peripheral circuit configured to perform a program operation on the memory cell array; and a control logic configured to control the peripheral circuit to coding-program one or more drain select transistors included in each of the plurality of memory blocks.