Semiconductor Memory Device Segmented Source Lines
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Solution Overview
Problem
Conventional semiconductor memory devices with dynamic memory cells face challenges in reducing layout size due to the need for periodic refresh of charged capacitors and the use of floating body transistors, which require a common ground voltage applied to all memory cells, limiting flexibility in write and read operations.
Innovation Solution
The semiconductor memory device employs separately arranged source lines instead of a common source diffusion layer, allowing for independent voltage control of source lines during write and read operations, enabling the use of capacitor-less dynamic memory cells and improving layout efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a common source diffusion layer is used to cover the entire substrate surface, then all memory cells can be connected to a fixed potential, but the layout size cannot be reduced and flexibility in voltage control is limited
Solution Approach 1:
The common source diffusion layer is segmented into multiple separate source lines (first source line, second source line, etc.) that are arranged in the first direction. Each source line can be independently controlled, allowing different voltage levels to be applied to different memory cell groups simultaneously. This segmentation resolves the contradiction by enabling both compact layout and flexible voltage control.
Solution Approach 2:
The source lines are transformed from a static common potential structure to dynamic independently controllable lines. By applying different voltages to different source lines during write and read operations, the system gains adaptability while maintaining compact layout. The first source line can receive a first voltage and the second source line can receive a second voltage, enabling flexible memory operations.
2Area of stationary object
If capacitor-less dynamic memory cells are used, then layout size can be reduced, but independent voltage control of source lines is required which increases device complexity
Solution Approach 1:
The memory cell array is divided into multiple groups, each group associated with a separate source line. This segmentation allows capacitor-less dynamic memory cells to be used while managing voltage control complexity through modular organization. Each source line serves a specific group of memory cells, reducing the overall control complexity compared to controlling all cells individually.
Solution Approach 2:
The separate source lines serve multiple functions: they provide voltage control for write operations, voltage control for read operations, and potential refresh operations. By making the source lines multi-functional and independently controllable, the patent reduces layout size with capacitor-less cells while managing the increased device complexity through versatile line utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more efficient memory operations by controlling voltages applied to source lines, reducing the need for periodic refresh and enhancing layout compactness, while maintaining data integrity through independent voltage management.
Implementation Method 1
A relatively large number of electron-hole pairs may be generated around the drain of the NMOS transistor by impact ionization. Of the electron-hole pairs, the electrons may be absorbed to the drain, and the holes may be stored in the floating body
Implementation Method 2
each memory cell MC may include a vertical MOS transistor formed with the pillar-type silicon layer 2. The transistor of each memory cell MC may be formed such that a gate insulating layer 3 may surround the pillar-type silicon layer 2
Data Source
AI summary
A semiconductor memory device and methods thereof. The example semiconductor memory device may include a semiconductor substrate, a first source line and a second source line oriented in a first direction, the first and second source lines not in contact with each other, at least one bit line oriented in the first direction and at least one drain positioned between the first and second source lines and the at least one bit line. A first example method may include applying a first voltage to a source line, connected to the memory cell, during a write operation of the memory cell and applying a second voltage to the source line during a read operation of the memory cell, the first and second voltages not being the same and the second voltage not being a ground voltage. A second example method may include applying a first positive voltage to a word line, applying a second positive voltage to a source line, detecting a voltage at a bit line, the detected bit line voltage based on the applied first and second positive voltages and determining whether the memory cell stores data at a first logic level or a second logic level based on the detected bit line voltage.