Memory Device Segregating Data by Importance Using Variable Bit Width
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Solution Overview
Problem
In neuromorphic computer systems and autonomous driving apparatuses, existing memory devices lack efficient data storage methods that consider the importance of data, leading to degraded reliability and operational efficiency due to uniform data programming across memory cells.
Innovation Solution
A memory device with a single semiconductor chip containing a first memory area for storing N-bit data and a second memory area for storing M-bit data, where M > N, allowing data to be stored based on importance, using separate access schemes and sharing an input and output interface, with a controller applying weights to sensing data and storing it accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single memory cell array is used to store all data with fixed bit width, then the memory structure is simple, but the reliability and operational efficiency degrade when data importance varies
Solution Approach 1:
The memory device is divided into multiple memory cell arrays (first memory cell array for N-bit data, second memory cell array for M-bit data) with different storage capacities. This segmentation allows data to be stored according to importance, with critical data in higher-capacity arrays, thereby improving reliability without requiring a completely new memory architecture.
Solution Approach 2:
Different memory cell arrays are assigned different data widths (N-bit vs. M-bit) to match the specific requirements of different data types. Important data that requires higher precision or larger storage capacity is stored in the second memory cell array with M-bit capacity, while less critical data uses the first memory cell array with N-bit capacity, optimizing both reliability and resource utilization.
2Productivity
If all memory cells are programmed using a single method, then the programming process is simple, but operational efficiency degrades when data importance varies
Solution Approach 1:
The memory device implements separate programming methods for different memory cell arrays. The first memory cell array uses a first programming method optimized for N-bit data, while the second memory cell array uses a second programming method optimized for M-bit data. This allows each array to be programmed efficiently according to its specific requirements, improving overall operational efficiency.
Solution Approach 2:
Different programming parameters and schemes are applied to different memory cell arrays based on data importance and required data width. The controller selects appropriate programming parameters (such as voltage levels, pulse widths, and programming algorithms) for each array, enabling optimized programming performance for different data types without requiring a complete redesign of the programming interface.
3Adaptability or versatility
If multiple memory chips are used to provide different data width storage, then storage flexibility improves, but device complexity and power consumption increase
Solution Approach 1:
Multiple memory cell arrays with different data widths (N-bit and M-bit) are integrated into a single memory device chip. This merging approach provides the storage flexibility of having different capacity options while avoiding the increased complexity and power consumption associated with multiple separate chips. The arrays share common control logic and interface circuits, reducing overall device complexity.
Solution Approach 2:
The memory device is designed with multi-functional capability to store data of different widths and importances within a single chip architecture. The controller can selectively access different memory cell arrays based on data requirements, providing versatile storage options. This universal design eliminates the need for multiple specialized chips while maintaining adaptability to different storage needs.
4Productivity
If a single memory area is used for all data, then the interface structure is simple, but storage efficiency decreases when data importance varies
Solution Approach 1:
The memory device is segmented into distinct memory areas (first memory cell array and second memory cell array) with different storage capacities suited for different data types. This segmentation enables efficient storage allocation where important data occupies the higher-capacity second array, improving storage efficiency. The segmented structure is managed by a unified controller that handles access to both areas through a single interface.
Solution Approach 2:
Each memory area is optimized with specific characteristics (N-bit vs. M-bit storage capacity) to match the requirements of different data types. The first memory area is optimized for smaller data units while the second memory area provides enhanced capacity for critical data. This local optimization improves overall storage efficiency without requiring a completely different interface structure, as the controller manages access to both areas efficiently.
Data Source
AI summary
A memory device comprises a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data, where N is a natural number, and a first peripheral circuit for controlling the first memory cells according to an N-bit data access scheme and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells according to an M-bit data access scheme and disposed below the second memory cell array, wherein the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight, wherein the plurality of first memory cells and the plurality of second memory cells are included in a first chip having a first metal pad, the first peripheral circuit and the second peripheral circuit are included in a second chip having a second metal pad, and the first chip and the second chip are vertically connected to each other by the first metal pad and the second metal pad.