Memory Device Read Reliability via Selective Bitline Masking

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current memory devices face challenges in improving the reliability of read operations due to noise phenomena caused by adjacent bit lines, which affect the accuracy and efficiency of data retrieval.

Innovation Solution

The memory device employs a control logic system that performs specific sensing operations and masking processes on memory cells with varying threshold voltage levels, ensuring accurate data read by controlling the peripheral circuits to apply appropriate voltages and masking processes during read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a standard read operation is performed on memory cells, then data retrieval is achieved, but noise interference from adjacent bit lines reduces read reliability

Engineering Contradiction:
Improveread operation reliabilityVSAvoidnoise interference from adjacent bit lines
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The read operation is segmented into multiple phases: a first sensing operation to identify memory cells requiring masking, a masking operation to isolate those cells, and a third sensing operation to read the remaining cells. This segmentation allows selective application of masking voltages to specific bit lines, reducing noise interference from adjacent bit lines during the main read operation and improving read reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs a preliminary sensing operation before the main read operation to identify which memory cells require masking. Based on the results of this preliminary sensing, masking voltages are applied in advance to specific bit lines before the main read operation begins. This preliminary action prevents noise interference from affecting the main read operation, thereby improving read reliability.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If masking process is applied to all memory cells during read operation, then noise interference is reduced, but read operation complexity increases

Engineering Contradiction:
Improveread operation reliabilityVSAvoidread operation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Instead of applying masking voltages uniformly to all bit lines, the patent applies masking voltages selectively only to those bit lines that are determined to require masking based on preliminary sensing results. This local quality approach ensures that masking is applied only where necessary to reduce noise interference, avoiding unnecessary complexity in the read operation while maintaining read reliability.

Inventive Principle:
Principle #3Local quality

3Measurement precision

If multiple sensing operations are performed, then accurate data retrieval is achieved, but read operation time increases

Engineering Contradiction:
Improvedata retrieval accuracyVSAvoidread operation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs a preliminary sensing operation on all memory cells to identify which ones require masking, but then only applies masking and performs additional sensing operations on the specific subset of cells that need it. This partial action approach ensures accurate data retrieval for cells requiring masking while avoiding unnecessary operations on cells that do not require masking, thus minimizing the increase in read operation time.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11195586B2Memory device and operating method of the memory device
Publication Date: 2021.12.07 SK HYNIX INC
  • US11195586B2 patent drawing
  • US11195586B2 patent drawing
  • US11195586B2 patent drawing

AI summary

A memory device and a method of operating the memory device are provided. The memory device includes a memory cell array including memory cells that are programmed into a plurality of program states, a peripheral circuit configured to perform a read operation on the memory cell array, and control logic configured to control the peripheral circuit to perform the read operation and to control the peripheral circuit to perform a masking process on first memory cells having a threshold voltage level higher than a first read level and second memory cells having a threshold voltage level lower than a second read level among the memory cells during the read operation.