Memory Device Verification Time Reduction via Selective Precharge
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Solution Overview
Problem
The existing memory devices face performance degradation due to the increased time required for data dumping operations during verification, which prolongs the program time.
Innovation Solution
The memory device incorporates control logic that manages the verification operation by controlling the page buffer circuit, allowing for selective precharging of bit lines and performing dump operations in both a dump section and a verification section to optimize the precharge process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data dumping operations are performed multiple times during verification, then verification accuracy is improved, but program time increases
Solution Approach 1:
The patent performs preliminary data dumping operations during the dump section before the verification section begins. By dumping data from data latches to sensing latches in advance, the verification process can proceed more quickly without sacrificing accuracy, thus reducing the overall program time while maintaining verification reliability
Solution Approach 2:
The verification process is divided into two distinct sections: a dump section for data preparation and a verification section for actual verification. This segmentation allows data dumping operations to be performed in parallel with other initialization activities during the dump section, and then focuses the verification section solely on the verification task, reducing total program time
2Speed
If all bit lines are precharged during verification, then verification speed is improved, but power consumption increases
Solution Approach 1:
The patent implements selective bit line precharging where only the bit lines corresponding to the specific program state being verified are precharged, rather than precharging all bit lines. This localized approach maintains verification speed for the relevant bit lines while significantly reducing power consumption by avoiding unnecessary precharging of unrelated bit lines
Data Source
AI summary
A memory device includes a memory cell array having memory cells therein that are programed to a plurality of program states, and a page buffer circuit having a plurality of page buffers therein that are connected to a plurality of bit lines associated with the memory cell array. Each of the page buffers includes a sensing latch that is connected to a corresponding one of the plurality of bit lines, and is configured to control a precharge operation performed on a corresponding bit line. Control logic is provided to control a verification operation performed on the plurality of program states within the memory cells by controlling the page buffer circuit, a plurality of dump operations on the sensing latch, which are based on values of at least two bits stored in each of the page buffers, and a selective precharge of bit lines that are connected to memory cells to be programmed to a first program state to be verified, from among the plurality of program states.