Memory Device Self-Degradation Detection and Mitigation

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Solution Overview

Problem

Memory devices face degradation due to wear and imprint effects, making it challenging to maintain performance and lifespan, especially when different types of memory media are connected to a single bus, requiring effective mitigation strategies that do not rely on host device communication.

Innovation Solution

A memory device with control circuitry that tracks operation counts and environmental factors to trigger remedial actions, such as wear-leveling and refresh operations, independently of the host device, to mitigate degradation and adjust operating characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memory devices track operation counts and trigger remedial actions independently, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvememory device reliabilityVSAvoidcontrol circuitry complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory device performs self-diagnosis and self-repair by independently tracking operation counts and triggering remedial actions without host intervention. The control circuitry monitors wear indicators and automatically executes wear-leveling or refresh operations to mitigate degradation, enabling the device to service itself and maintain reliability.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system performs preliminary detection of degradation trends by tracking operation counts before critical failure occurs. By monitoring wear indicators in advance and triggering remedial actions proactively, the memory device prevents catastrophic failure and extends its operational lifespan through early intervention.

Inventive Principle:
Principle #10Preliminary action

2Duration of action of moving object

If remedial actions are triggered based on operation counts, then lifespan is extended, but productivity decreases

Engineering Contradiction:
Improvememory device lifespanVSAvoidoperational throughput
Core Design Contradiction:
Duration of action of moving objectVSProductivity

Solution Approach 1:

The control circuitry implements periodic monitoring of operation counts and triggers remedial actions at predetermined intervals based on accumulated wear. This periodic approach allows the memory device to maintain normal high-speed operations between checks while periodically performing wear-mitigation tasks, balancing lifespan extension with sustained productivity.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system continuously tracks operation counts in the background without interrupting normal memory operations. Remedial actions are scheduled to execute during idle periods or low-utilization windows, ensuring that wear-mitigation activities do not significantly impact overall operational throughput while maintaining continuous protection against degradation.

Inventive Principle:
Principle #20Continuity of useful action

3Adaptability or versatility

If independent degradation detection is implemented, then adaptability is improved, but device complexity increases

Engineering Contradiction:
Improvemulti-memory type supportVSAvoidcontrol circuitry complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The control circuitry is designed with universal functionality to support multiple memory device types (e.g., NAND, NOR, 3D cross-point) through a unified degradation detection and remediation framework. By implementing operation count tracking and wear-leveling algorithms that adapt to different memory technologies, the system achieves multi-memory type support without requiring separate specialized circuits for each device type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11393543B2Methods for detecting and mitigating memory media degradation and memory devices employing the same
Publication Date: 2022.07.19 MICRON TECHNOLOGY INC
  • US11393543B2 patent drawing
  • US11393543B2 patent drawing
  • US11393543B2 patent drawing

AI summary

Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.