Semiconductor Memory Device Shielding Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor memory devices, the presence of a dummy cell adjacent to a reference cell can cause variations in current or voltage values due to parasitic capacitance, making it difficult to determine whether data is '0' or '1' when accessing a memory cell, and existing solutions that use a shield line increase the device area.
Innovation Solution
A semiconductor memory device configuration where a third main bit line is used as a shield by being set to ground potential, electrically isolated from other selection transistors, to prevent influence from adjacent main bit lines without requiring a new shield line, thereby maintaining device area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dummy cell is disposed adjacent to the reference cell to prevent leakage current, then leakage current prevention is improved, but parasitic capacitance between main bit lines causes variations in reference cell current/voltage values making data determination difficult
Solution Approach 1:
A third main bit line is introduced as an intermediary element between the first main bit line (connected to reference cell) and the second main bit line group (connected to core cells). This third main bit line acts as a shield line that blocks parasitic capacitance coupling from the second main bit line group to the first main bit line, thereby preventing variations in reference cell current/voltage values while maintaining the dummy cell configuration for leakage current prevention
2Measurement precision
If a shield line is disposed between the reference main bit line and other main bit lines to prevent parasitic capacitance influence, then measurement precision is improved, but device area increases
Solution Approach 1:
The third main bit line serves multiple functions simultaneously: it acts as a signal transmission line for the third memory cell and as a shield line blocking parasitic capacitance between the first main bit line and the second main bit line group. This multi-functionality achieves shielding without requiring an additional dedicated shield line, thereby preventing area increase
Solution Approach 2:
The shielding function is merged with the signal transmission function by using the third main bit line (which connects to the third memory cell) as both a signal line and a shield line. This consolidation eliminates the need for separate shield lines while maintaining shielding effectiveness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively shields the reference main bit line from parasitic capacitance effects without increasing the device area, ensuring accurate data determination without the need for additional shield lines.
Implementation Method 1
a main bit line connected to the dummy cell is adjacent to a main bit line connected to the reference cell. This causes a problem where when, for example, the dummy cell is accessed, the main bit line of the reference cell may be influenced, under the influence of a parasitic capacitance between the main bit lines
Data Source
AI summary
A main bit line is disposed between a reference main bit line and core main bit lines. A selection transistor disposed between a sub bit line connected to a cell and the main bit line can switch between a conductive state and a non-conductive state independently of other selection transistors. A dummy main bit line can be set to ground potential by a shield grounding section, and can be used as a shield line of the reference main bit line.