Semiconductor Memory Device Signal Line Layout Structure
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in reducing operating current while maintaining data bandwidth, as increasing page size optimizes area but increases current consumption, and reducing page size increases area and power supply requirements.
Innovation Solution
The semiconductor memory device divides the memory bank into two or more regions, with independently operable memory blocks, using a hierarchical word line structure and selectively enabling bit line sense amplifiers and data transmission lines to reduce current consumption without increasing the number of signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the page size is increased to optimize area and increase the number of net dies, then the area efficiency is improved, but the operating current increases due to more bit line sense amplifiers being operated
Solution Approach 1:
The memory bank is divided into multiple memory blocks (first memory block, second memory block, etc.), each with its own bit line sense amplifiers and data transmission lines. This segmentation allows selective operation of individual blocks, enabling the system to maintain larger overall area while operating only the necessary portions, thus reducing current consumption.
Solution Approach 2:
The system dynamically selects and activates specific memory blocks and their associated bit line sense amplifiers based on the required data bandwidth. The column decoder generates column select signals that enable only the necessary memory blocks for each operation, allowing the operating current to be adjusted dynamically according to actual needs rather than always operating at maximum capacity.
2Use of energy by moving object
If the page size is reduced to decrease operating current, then the current consumption is reduced, but the area of the memory device increases
Solution Approach 1:
By segmenting the memory bank into multiple blocks, the system can maintain a compact overall area while providing the capability to operate smaller subsets (effectively smaller page sizes) when needed. The physical layout remains area-efficient, but the operational granularity is reduced through block segmentation.
Solution Approach 2:
Different memory blocks can be selectively activated based on local requirements. The system applies different operational characteristics to different parts of the memory bank, enabling current reduction in inactive blocks while maintaining full area utilization potential when all blocks are needed.
3Productivity
If more bit line sense amplifiers are operated to handle larger page sizes, then the data bandwidth is increased, but the operating current increases
Solution Approach 1:
The system provides dynamic control over the number of active bit line sense amplifiers through the column decoder and column select signals. Data bandwidth can be scaled dynamically by activating different numbers of memory blocks, allowing the system to match current consumption to actual bandwidth requirements rather than operating at fixed maximum capacity.
Solution Approach 2:
The segmentation of memory blocks with dedicated bit line sense amplifiers allows the system to achieve high data bandwidth when needed by activating multiple blocks, while reducing current consumption by activating fewer blocks when lower bandwidth suffices. Each block acts as an independent unit that can be selectively enabled.
Data Source
AI summary
A memory device includes first and second memory blocks each including a memory cell array, a sub-word line drive region and a bit line sense amplifier region corresponding to the memory cell array, first and second data transmission lines disposed in the bit line sense amplifier region of each memory block, wherein the first and second data transmission lines extend on an identical row and transmit data of the memory cell array of the memory block, a row decoder configured to select one of the first and second memory blocks in response to a row address and enable a word line of the memory cell array included in the selected memory block, and a column decoder configured to generate, in response to a column address, first and second column select signals corresponding to the first and second data transmission lines of the bit line sense amplifier region.