Memory Device Signal Logging for PoP Error Detection
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Solution Overview
Problem
Semiconductor memory devices, especially those in embedded systems with Package on Package (PoP) form, face challenges in detecting errors due to internal pins not being exposed, making it difficult to observe signals and detect faults using conventional logic analyzers.
Innovation Solution
A memory device with first and second memory cell arrays and controllers that log command and address signals during operation, allowing for error analysis by writing and reading these signals to a memory cell array, enabling error detection and logging even in non-exposed internal pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If internal pins are not exposed in PoP form, then device integration is improved, but error detection capability deteriorates
Solution Approach 1:
The patent creates a copy of the internal pin signals by logging command signals and address signals to a separate memory cell array. This logged copy can be read and analyzed externally without exposing the actual internal pins, thus maintaining device integration while enabling error detection through analysis of the copied signal data.
2Difficulty of detecting and measuring
If logic analyzer probes are connected to pins, then error detection is improved, but device operation is disrupted
Solution Approach 1:
The patent performs preliminary action by logging the command signals and address signals to a memory cell array before any error analysis is needed. This allows the device to operate normally during logging, and the logged data can be analyzed later without disrupting device operation, thus improving error detection while maintaining ease of operation.
3Measurement precision
If all pins are exposed for observation, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts only the necessary signal information (command signals and address signals) and stores it in a separate memory cell array, rather than exposing all pins for observation. This selective extraction maintains measurement precision for the critical signals while reducing device complexity by avoiding the need to expose and route all internal pins externally.
Data Source
AI summary
A memory device includes first and second memory cell arrays, a first controller, and a second controller. The first controller controls the first memory cell array through first word line signals and first bit line signals to execute an operation corresponding to a command signal based on an address signal and a data signal. The second controller includes first and second mode registers. The second controller writes sampled values of the address signal and the command signal to the second memory cell array through access signals to form a log in response to stored values of the first and second mode registers or reads stored values of the second memory cell array as the data signal through the access signals.