Semiconductor Memory Device Signal Processing for Write Postamble Ringing
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Solution Overview
Problem
Conventional methods for preventing write postamble ringing in semiconductor memory devices fail to accurately determine the completion point of a write operation due to domain skew between the clock and data strobe signals, leading to increased signal delay and current consumption during high-speed operations.
Innovation Solution
A semiconductor memory device with a signal processing unit that generates a control signal based on burst length information and a monitoring unit to determine the activation of the control signal, along with an output controlling unit that stops the data strobe signal output period in response to a filtering signal, ensuring proper filtering and minimizing ringing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a filtering signal is generated in the clock domain to limit the data strobe signal output period, then write postamble ringing can be prevented, but domain skew occurs between the clock and data strobe signals leading to inaccurate filtering
Solution Approach 1:
A domain conversion unit is introduced as an intermediary to convert the clock domain filtering signal into the data strobe signal domain. This mediator resolves the domain skew issue by translating the filtering control from the clock domain to the data strobe domain, ensuring accurate timing alignment without direct domain conflicts
Solution Approach 2:
The completion point of the write operation is determined in advance using the data strobe signal before generating the filtering signal. This preliminary determination ensures that the filtering signal is generated with accurate timing reference, preventing domain skew issues and enabling precise filtering control
2Measurement precision
If domain synchronization is performed to address skew between clock and data strobe signals, then filtering accuracy improves, but signal delay increases and current consumption rises
Solution Approach 1:
The domain conversion unit serves as an efficient intermediary that converts signals between domains without requiring complex continuous synchronization mechanisms. This approach achieves necessary timing accuracy only at critical points (write operation completion), reducing overall synchronization overhead and current consumption
Solution Approach 2:
Domain conversion and timing alignment are performed preliminarily at the write operation completion point rather than continuously during the entire operation. This preliminary action approach achieves the necessary filtering accuracy while minimizing the duration and intensity of domain synchronization activities, thereby reducing current consumption
3Measurement precision
If domain synchronization is performed to ensure accurate filtering, then filtering precision improves, but signal delay increases reducing high-speed operation capability
Solution Approach 1:
The domain conversion and timing alignment are performed preliminarily and in advance, specifically at the write operation completion point. This allows the filtering signal to be generated with accurate timing reference before the actual filtering is needed, eliminating the need for delayed synchronization and maintaining high-speed operation
Solution Approach 2:
The domain conversion unit acts as an efficient intermediary that performs rapid domain translation without introducing significant delay. By converting the filtering signal to the data strobe domain at the precise completion point, it achieves accurate filtering alignment while maintaining the high-speed signal flow required for high-speed memory operations
Data Source
AI summary
A semiconductor memory device includes a signal processing unit configured to generate a control signal corresponding to burst length information and an output controlling unit configured to control an output of a data strobe signal in response to the control signal.