Memory Device Signed Multiplication Logic States
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Solution Overview
Problem
The limited memory bandwidth and power consumption issues in deep learning applications, particularly in edge AI systems, due to the bottleneck of inter-chip data movement and the inefficiency of conventional Von-Neumann computer architecture, hinder the performance of AI tasks like image processing and neural network computations.
Innovation Solution
An integrated circuit device that combines memory and processing, using a memory cell array to perform inference computations efficiently by reducing matrix vector multiplication to a memory access function and parallelizing accumulation operations, allowing for efficient matrix vector multiplication and accumulation in an array of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transmitted from sensors to microprocessors for processing, then computation can be performed, but transmission bandwidth and power consumption increase
Solution Approach 1:
The patent merges memory and processing functions into a single integrated device. Memory cells are configured to perform multiplication operations natively, eliminating the need to transfer data between separate memory and processing units. This integration directly reduces power consumption associated with data transmission while maintaining computation capability.
Solution Approach 2:
The memory device performs computation operations autonomously without requiring external microprocessors. The memory cells themselves execute multiplication and accumulation operations using their stored data, enabling the system to process information where it is stored, thereby eliminating bandwidth-consuming data transfers.
2Productivity
If data is transmitted from sensors to microprocessors for processing, then computation can be performed, but transmission bandwidth requirements increase
Solution Approach 1:
The patent merges memory and processing functions into a single integrated device. Memory cells are configured to perform multiplication operations natively, eliminating the need to transfer data between separate memory and processing units. This integration directly reduces power consumption associated with data transmission while maintaining computation capability.
Solution Approach 2:
The memory device performs computation operations autonomously without requiring external microprocessors. The memory cells themselves execute multiplication and accumulation operations using their stored data, enabling the system to process information where it is stored, thereby eliminating bandwidth-consuming data transfers.
3Device complexity
If conventional Von-Neumann architecture is used, then system simplicity is maintained, but computational efficiency decreases
Solution Approach 1:
The patent replaces the conventional Von-Neumann architecture with a memory-centric computing approach. Instead of using general-purpose microprocessors to perform computations, the system uses memory cells configured to execute multiplication and accumulation operations directly, substituting traditional processing mechanics with memory-based computation.
Solution Approach 2:
The patent changes the operational parameters of memory cells to enable computation. By configuring memory cells to perform multiplication operations and using bitline currents to accumulate results, the system transforms standard memory components into computational units, fundamentally altering how processing is performed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and increases computational efficiency by integrating memory and processing, enabling faster and more accurate AI computations with reduced latency and bandwidth limitations.
Implementation Method 1
When a voltage representative of a predetermined value is applied on a memory cell, an electrical current outputs from the memory cell, the electrical current being a multiple of a predetermined amount of current
Data Source
AI summary
Systems, methods, and apparatus related to memory devices that perform signed multiplication using logical states of memory cells. In one approach, a memory device has a memory array including sets of memory cells programmed to store a signed weight in each set (e.g., four cells in a set store a signed weight of +1, 0, or −1). Voltages that represent signed inputs (e.g., +1, 0, or −1) are applied to the memory cells to perform the multiplication. A result from the multiplication is determined based on summing of output currents from the memory cells.