Semiconductor Memory Device Global Line Skew Reduction
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Solution Overview
Problem
The existing semiconductor memory devices experience data skew due to differences in global line lengths between banks, leading to deteriorated CAS to CAS Delay (tCCD) characteristics, as physical locations of banks result in varying line loading and delayed data access.
Innovation Solution
The semiconductor memory device incorporates a configuration with dedicated local lines and shared sub-global lines, along with data intervention blocks and control circuits that manage bank strobe signals and delayed write/read strobe signals to reduce global line length and maintain local line length, thereby minimizing data skew during write and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If banks share a common global line, then device complexity is reduced, but data skew occurs due to different line loading in banks at different physical locations
Solution Approach 1:
The global line is segmented into multiple sub-global lines, with each sub-global line serving a specific bank or group of banks. This segmentation allows each sub-global line to be optimized for its specific physical location and loading characteristics, thereby reducing data skew while maintaining the benefits of shared global line architecture.
Solution Approach 2:
Different sub-global lines are designed with different characteristics (length, routing, buffering) according to the specific requirements of each bank's physical location. This local optimization ensures that each bank receives data with appropriate timing and quality, reducing overall data skew in the system.
2Loss of time
If the global line length is reduced, then data access time is improved, but dedicated local line length must be maintained which conflicts with space optimization
Solution Approach 1:
The data path is segmented into sub-global lines for time-critical data transmission and dedicated local lines for stable, length-maintained connections. This allows the system to optimize data access time through shorter sub-global lines while preserving the integrity and timing characteristics of dedicated local lines.
Solution Approach 2:
Data intervention blocks serve as intermediary components between sub-global lines and dedicated local lines. These blocks can buffer, delay, or forward data as needed, allowing the system to maintain optimal timing for both short sub-global lines and longer dedicated local lines without conflict.
3Manufacturing precision
If data intervention blocks are added to manage timing, then data skew is reduced, but device complexity increases
Solution Approach 1:
Data intervention blocks are positioned strategically along the data path to preemptively correct timing issues before data reaches banks with different loading characteristics. By applying timing adjustments in advance, the system reduces data skew without requiring complex real-time control mechanisms.
Solution Approach 2:
Each data intervention block autonomously manages timing for its associated sub-global line based on predetermined characteristics, without requiring centralized control. This distributed self-service approach reduces data skew while minimizing overall system complexity.
Data Source
AI summary
A semiconductor memory device includes a plurality of banks each having a dedicated line and sharing a global line, a plurality of sub-global lines shared by neighboring banks among the plurality of banks, a plurality of data input/output circuits coupled to the plurality of banks, respectively, through the dedicated line and coupling the dedicated lines of corresponding banks to the sub-global lines in response to bank strobe signals, respectively, and a plurality of data intervention blocks corresponding to the plurality of sub-global lines, respectively, and coupling the global line to corresponding sub-global lines in response to a delayed write strobe signal or read strobe signals.