Memory Device Sleep Mode Data Restoration
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Solution Overview
Problem
In memory devices with non-volatile memory, the transition from sleep mode to normal mode is hindered by the need to restore power and data, leading to prolonged return times and increased NAND memory access, which can shorten its lifespan.
Innovation Solution
A memory device with a controller that saves register information and firmware in the host's main memory before entering sleep mode, allowing for quicker restoration and reduced NAND access upon returning to normal mode, utilizing a power supply circuit to shut off power to unnecessary components during sleep mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory device restores all data from NAND memory when returning from sleep mode, then data integrity is ensured, but the return time is prolonged and NAND memory lifespan is reduced
Solution Approach 1:
The system performs preliminary actions by saving critical register information and firmware to the host's main memory before entering sleep mode. When returning from sleep mode, the device can quickly restore from this pre-saved data rather than reading from NAND memory, thus ensuring data integrity while significantly reducing return time and NAND access frequency.
2Reliability
If the memory device accesses NAND memory frequently for data restoration, then data recovery is complete, but the lifespan of NAND memory is shortened
Solution Approach 1:
The invention extracts critical data (register information and firmware) from the NAND memory system and stores it in the host's main memory during normal operation. Before sleep mode, this data is saved to main memory again. Upon waking, the device restores from this extracted copy rather than accessing NAND memory, thus ensuring complete data recovery while minimizing NAND memory access and extending its lifespan.
3Loss of time
If the controller saves register information in host memory, then return time is shortened, but device complexity increases
Solution Approach 1:
The host's main memory acts as an intermediary between the NAND memory and the controller's registers. Instead of the controller directly managing all data restoration from NAND, it saves critical information to this intermediary storage location before sleep mode. This intermediary approach shortens return time while distributing complexity to the host system rather than concentrating it in the memory device.
Data Source
AI summary
According to one embodiment, when shifting to a sleep mode, a processor of a memory device transmits a first command and saving data to a host and issues a power shut-off request. The first command is a command for writing data to a first memory of the host. The saving data includes register information. The register information includes register data stored in the control register and an address of the control register. A power supply circuit shuts off power supply to a second memory of the memory device, the control register, the processor, and a peripheral circuit in response to the issued power shut-off request.