Semiconductor Memory Device Slit Formation Method
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in ensuring high reliability due to complexities in the manufacturing process, particularly in forming slits that isolate memory blocks, which can lead to variations in slit depth and shape, resulting in increased failure rates.
Innovation Solution
The semiconductor memory device employs a manufacturing method where the conductive layer with high etching difficulty is worked before stacking insulating layers, using a sacrificial layer and protective layers to form slit grooves that are etched to specific depths, facilitating precise control over slit formation and reducing failure rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If slits are formed to isolate memory blocks in conventional manufacturing, then memory block isolation is achieved, but variations in slit depth and shape occur leading to increased failure rates
Solution Approach 1:
The patent applies preliminary action by forming the conductive layer with high etching difficulty before stacking the insulating layers. This allows the slit grooves to be etched to a predetermined depth through the insulating layers and into the conductive layer, ensuring consistent depth and shape while isolating memory blocks effectively.
Solution Approach 2:
The patent segments the manufacturing process into distinct stages: first forming the conductive layer, then stacking insulating layers, and finally etching slit grooves to specific depths. This segmentation allows precise control over slit formation by working with individual layers separately, improving depth and shape consistency.
2Manufacturing precision
If the conductive layer with high etching difficulty is worked before stacking insulating layers, then precise control over slit formation is achieved, but the manufacturing process becomes more complex
Solution Approach 1:
The conductive layer is prepared in advance before insulating layers are stacked, establishing a foundation for precise slit formation. This preliminary preparation includes forming the layer with specific properties that facilitate controlled etching, enabling subsequent precise slit creation without excessive process complexity.
Solution Approach 2:
The patent applies local quality by treating the conductive layer with specific characteristics in the regions where slits will be formed. The etching process targets specific areas with predetermined depths, allowing precise local control over slit formation while maintaining overall process manageability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of the semiconductor memory device by improving the precision and consistency of slit formation, thereby reducing failure occurrences and maintaining desired shapes, leading to improved device performance.
Implementation Method 1
the conductive layer with high etching difficulty is worked before stacking insulating layers, using a sacrificial layer and protective layers to form slit grooves that are etched to specific depths
Data Source
AI summary
According to one embodiment, semiconductor memory device includes a first conductive layer, a plurality of second conductive layers stacked over the first conductive layer in a first direction, a memory pillar extending in the plurality of second conductive layers in the first direction, and a first layer extending from the first conductive layer through a portion of the plurality of second conductive layers in the first direction in contact with a the plurality of second conductive layers, the first layer including a first portion having a first cross section in the plane of second and third directions that are perpendicular to each other and to the first direction, and a second portion having a second cross section, different from the first cross section, in the plane of the second and third directions.