Semiconductor Memory Device Optimized Spacing
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing storage density while maintaining low resistance in conductive layers, as narrow spacing between memory portions can lead to void formation and increased resistance, and excessive spacing decreases memory density.
Innovation Solution
A semiconductor memory device is designed with a stacked body containing conductive layers arranged in a specific configuration, where the spacing between memory portions is optimized to be longer than the pitch but shorter than twice the pitch, allowing for easy material introduction and reducing void formation, thereby increasing density and maintaining low resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the spacing between memory portions is reduced to increase storage density, then storage density is improved, but void formation increases and resistance increases
Solution Approach 1:
The patent applies parameter changes by optimizing the spacing between memory portions to a specific range (greater than pitch but less than twice the pitch). This parameter optimization resolves the contradiction by finding the optimal balance point where storage density is maximized while preventing void formation that would increase resistance. The conductive layer thickness is also adjusted to maintain appropriate ratios with the spacing dimensions.
Solution Approach 2:
The patent applies local quality by creating different structural characteristics in different regions. Specifically, the insulating portion is positioned adjacent to conductive layers at specific locations where void formation is most problematic, providing localized reinforcement to prevent voids in critical areas while maintaining narrow spacing overall for high density.
2Reliability
If the spacing between memory portions is increased to reduce void formation, then resistance is reduced, but storage density decreases
Solution Approach 1:
The patent resolves this contradiction through parameter changes by establishing an optimal spacing range (greater than pitch but less than twice the pitch) and adjusting conductive layer thickness to maintain appropriate ratios. This optimized parameter set achieves both low resistance and high storage density simultaneously, eliminating the need to choose between the two opposing requirements.
Solution Approach 2:
The patent introduces an insulating portion as an intermediary element positioned adjacent to conductive layers. This insulating portion acts as a mediator that prevents void formation at critical interfaces between memory portions and conductive layers, allowing narrow spacing to be maintained without the harmful effect of void-induced resistance increases.
3Quantity of substance
If narrow spacing is used to increase density, then storage density is improved, but material introduction becomes difficult and voids increase
Solution Approach 1:
The insulating portion serves as an intermediary structure that facilitates material introduction in narrow spacing configurations. By positioning the insulating portion adjacent to conductive layers, it creates a controlled interface that guides material deposition and prevents void formation, making the manufacturing process easier despite the narrow spacing requirements for high density.
Solution Approach 2:
The patent applies preliminary action by pre-positioning the insulating portion before final conductive layer formation. This preliminary structural arrangement prepares the interface to receive conductive material without void formation, ensuring easy material introduction and preventing defects before they can occur during the manufacturing process.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a stacked body, first memory portions, and second memory portions. The stacked body includes conductive layers. The conductive layers are arranged in a first direction and extend in a second direction. The stacked body includes first and second regions. The second region is arranged with the first region in the second direction. The first memory portions extend in the first direction through the first region and are arranged at a first pitch along the second direction. The second memory portions extend in the first direction through the second region and are arranged at the first pitch along the second direction. A distance between a first center of one of the first memory portions and a second center of one of the second memory portions is longer than the first pitch and shorter than 2 times the first pitch.