Memory Device Sparse Matrix Computation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory devices face inefficiencies in performing mathematical calculations, particularly with sparse matrices, due to hardware limitations that result in wasted computing resources as many operation units are programmed to represent zero elements, leading to suboptimal use of parallel computing capabilities.
Innovation Solution
The memory device rearranges matrices to cluster non-zero elements and generates a mapping table to optimize the distribution of sub-matrices across operation units, allowing for more efficient resource utilization by programming only non-zero elements, thereby reducing the number of operation units required for calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory device performs calculations using fixed operation units, then hardware architecture provides stable computing framework, but computing resource is wasted when calculating sparse matrices
Solution Approach 1:
The patent segments the matrix computation task by dividing the matrix into sub-matrices and further into non-zero element groups. Each operation unit is assigned to compute specific non-zero element groups rather than processing entire fixed-size matrix blocks. This segmentation allows the system to process only relevant data portions, improving resource utilization for sparse matrices while maintaining the fixed operation unit hardware structure.
Solution Approach 2:
The patent introduces dynamic configuration of operation units through a mapping table that dynamically assigns operation units to different non-zero element groups based on the input matrix characteristics. The mapping table is updated for each computation task, allowing the fixed hardware architecture to adapt dynamically to different matrix sparsity patterns and sizes, thereby optimizing computing resource utilization without changing the physical hardware structure.
2Productivity
If operation units are programmed to represent zero elements, then fixed hardware architecture is utilized, but computing efficiency decreases due to wasted operation units
Solution Approach 1:
The patent extracts and processes only the non-zero elements from the matrix by identifying their positions and values, then organizing them into groups that can be processed by operation units. Zero elements are completely excluded from the computation process. This extraction approach ensures that every operation unit processes meaningful data, eliminating the waste of computing efficiency that occurs when operation units are programmed to represent zero elements.
Solution Approach 2:
The patent changes the parameter representation from fixed matrix block dimensions to variable non-zero element group sizes. Instead of each operation unit handling a fixed-size matrix block (many of which contain zeros), the mapping table configures operation units to handle variable-sized groups containing only non-zero elements. This parameter change allows the system to reduce the effective number of operation units needed while maintaining full utilization of those that are active.
3Ease of operation
If matrix is processed in minimum operation unit, then hardware architecture constraint is satisfied, but resource waste occurs for sparse matrices with many zero elements
Solution Approach 1:
The patent performs preliminary actions by pre-processing the input matrix to identify non-zero element positions and values before the actual computation. The mapping table is constructed in advance to organize these non-zero elements into groups that can be efficiently processed by the fixed operation units. This preliminary organization ensures that when the hardware executes the computation, every operation unit receives meaningful data without wasting energy on zero elements, while still adhering to the minimum operation unit hardware constraint.
Solution Approach 2:
The mapping table serves as an intermediary between the fixed operation unit hardware architecture and the sparse matrix data. It translates the hardware's fixed operation unit structure into an optimized data organization that groups non-zero elements according to the operation units' capabilities. This intermediary layer allows the system to satisfy hardware architecture constraints while eliminating resource waste by ensuring that each operation unit processes only relevant non-zero elements.
Data Source
AI summary
Disclosed is a memory device and an operation method thereof. The operation method of memory device, comprising: programming a plurality of sub-matrices including at least one of non-zero element of a rearranged matrix to a plurality of operation units of the memory device; and programming a mapping table into a working memory of a memory device. The rearranged matrix is generated by rearrange a plurality of columns and a plurality of rows of an original matrix according to the positions of a plurality of non-zero elements of the original matrix. The mapping table comprises a correspondence of row indexes between the original matrix and the rearranged matrix, a correspondence of column indexes between the original matrix and the rearranged matrix and a correspondence between the sub-matrices including at least one non-zero element and the operation units storing the sub-matrices including at least one non-zero element.