3D Memory Device Vertical Stacking Layout Area Reduction
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Solution Overview
Problem
The challenge in semiconductor technology is to increase the number of planes in a memory device within a limited layout area while minimizing the consumption of layout space by row decoders and page buffer circuits, as the number of planes increases, leading to higher layout area consumption.
Innovation Solution
The solution involves stacking wafers vertically to overlap row and column drivers and operators across planes, allowing for a more efficient use of space by placing high-voltage transistors in one wafer and low-voltage transistors in another, and positioning logic circuits in the same wafer as planes or overlapping them vertically, thereby reducing the overall layout area occupied by the logic circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of planes is increased to improve memory capacity and performance, then the memory device can execute more simultaneous operations, but the layout area consumed by row decoders and page buffer circuits increases significantly
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture. Multiple memory planes are formed by stacking wafers vertically, allowing memory cells to be arranged in three dimensions. This vertical stacking enables more memory planes to be integrated within the same footprint area, improving density without proportionally increasing the layout area.
Solution Approach 2:
The patent merges the row decoder and page buffer circuits across multiple wafers. Specifically, row decoders are integrated into the first wafer while page buffer circuits are integrated into the second wafer, with inter-wafer connections establishing electrical pathways between them. This consolidation shares common circuitry across planes, reducing the total number of redundant circuits and minimizing the overall layout area required for support logic.
2Reliability
If row decoders and page buffer circuits are provided for each plane to ensure independent operation, then operational reliability is maintained, but the layout area consumption increases with the number of planes
Solution Approach 1:
The patent segments the support logic functions across different wafers: row decoders are segmented into the first wafer while page buffer circuits are segmented into the second wafer. This functional segmentation allows each wafer to be optimized independently while maintaining overall system reliability through distributed architecture and inter-wafer communication pathways.
Solution Approach 2:
The patent implements universal row decoder and page buffer circuits that serve multiple memory planes simultaneously. A single row decoder on the first wafer can decode row addresses for multiple planes, and a single page buffer circuit on the second wafer can buffer data from multiple planes. This multi-functionality reduces the total number of circuits needed compared to providing dedicated circuits for each plane, thereby reducing layout area while maintaining operational reliability.
Data Source
AI summary
A memory device includes a first plane defined in a second wafer stacked on a first wafer; a second plane defined in a third wafer stacked on the second wafer, and overlapping with the first plane in a vertical direction; a first page buffer circuit including a first column driver coupled to bit lines of the first plane and a first column operator; and a second page buffer circuit including a second column driver coupled to bit lines of the second plane and a second column operator. The first column driver is disposed in the second wafer, the second column driver is disposed in the third wafer and overlaps with the first column driver in the vertical direction, and the first and second column operators are disposed in a cell region of the first wafer and overlap with the first and second planes in the vertical direction.