Memory Device Successive Read Failure Prevention
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Solution Overview
Problem
Conventional memory devices experience failures due to gradual voltage differences between bit lines during successive read operations on the same memory cell, leading to incomplete recovery of voltage levels and potential data transmission failures.
Innovation Solution
A memory device with a blocking signal generation unit that detects successive read commands with the same address, activating a blocking signal to prevent data transmission from the memory array to the data bus, ensuring that previously loaded data is outputted through the transmitter, thereby maintaining voltage levels and preventing failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If successive read operations are performed on the same memory cell, then data can be continuously read from the memory device, but voltage levels on bit lines cannot be completely recovered leading to potential data transmission failures
Solution Approach 1:
The patent applies preliminary action by detecting successive read commands before they cause voltage recovery issues, and blocking data transmission in advance. The address comparator detects when the same address is accessed consecutively, and the blocking signal generation unit prevents data transmission before voltage levels can degrade, thus maintaining reliability while allowing continuous operations.
2Productivity
If data transmission is allowed during successive read operations, then productivity is maintained, but voltage differences between bit lines accumulate causing fails
Solution Approach 1:
The patent converts the harmful effect of voltage difference accumulation into a useful detection mechanism. By monitoring address patterns, the system identifies when successive reads occur and uses this information to block transmission, thereby preventing the harmful voltage accumulation while maintaining efficient operation during normal read sequences.
3Reliability
If a blocking signal is introduced to prevent voltage recovery issues, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent introduces intermediary components (address comparator and blocking signal generation unit) that mediate between the read command input and the data transmission output. These intermediaries add minimal complexity by only activating when specific address patterns are detected, providing reliable failure prevention without significantly increasing overall device complexity.
Data Source
AI summary
A memory device include a memory array, a transmitter suitable for outputting data to the outside of the memory device, and a data bus suitable for transmitting data of a selected memory cell in the memory array to the transmitter during a read operation. When successive read commands for the same memory cell are applied, data transmission from the memory array to the data bus is blocked, and data previously loaded in the data bus is outputted through the transmitter.