Semiconductor Memory Device Parallel Test Terminal Merging
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Solution Overview
Problem
Conventional semiconductor memory devices face limitations in the number of chips that can be tested in parallel and increased manufacturing costs due to a large number of data input/output terminals, which necessitate a significant number of wirings and terminals on the probe card.
Innovation Solution
A semiconductor memory device with a memory cell array, multiple data input/output terminals, signal paths for parallel data writing, latch circuits to temporarily hold data, and a selector circuit to selectively supply data during testing, reducing the number of terminals required for the probe card.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of data input/output terminals per chip is increased to achieve higher data I/O width, then the data processing capability is improved, but the number of wirings and terminals required on the probe card increases significantly
Solution Approach 1:
The patent combines multiple data terminals into a single composite terminal structure. Specifically, multiple data input terminals are merged into one composite data input terminal, and multiple data output terminals are merged into one composite data output terminal. This merging reduces the number of separate wirings required on the probe card while maintaining the capability to handle multiple data bits in parallel through internal switching and latching mechanisms.
Solution Approach 2:
The patent introduces intermediary components including a composite terminal, a selector circuit, and latch circuits that act as mediators between the reduced probe card terminals and the multiple data paths. The selector circuit selectively connects the composite terminal to different data terminals, while latch circuits temporarily hold data values, enabling multiple data bits to be transmitted through fewer external terminals.
2Reliability
If the number of terminals on the probe card is increased to support more data input/output terminals, then the testing capability for high-width data buses is improved, but the manufacturing cost increases
Solution Approach 1:
The patent merges multiple data terminals into composite terminals to reduce the total number of probe card terminals required. This merging maintains full testing capability for high-width data buses by using internal selector and latch circuits to manage multiple data paths, thereby reducing manufacturing costs associated with creating and managing a large number of probe card terminals.
Solution Approach 2:
The composite terminal and associated selector/latch circuits provide multi-functionality, allowing a single terminal structure to handle multiple data bits and support various testing operations. This universal structure can test different data widths and patterns without requiring separate dedicated terminals for each function, improving testing capability while controlling costs.
3Productivity
If the number of chips tested in parallel is increased to improve manufacturing efficiency, then the productivity is improved, but the number of wirings required on the probe card increases
Solution Approach 1:
The patent merges data terminals across multiple chips by providing a single composite data input terminal and composite data output terminal that serve multiple chips in parallel. The internal selector circuit can selectively connect this composite terminal to data terminals of different chips, and latch circuits hold data values for parallel operations, enabling multiple chips to be tested simultaneously with fewer external wirings.
Solution Approach 2:
The patent employs dynamic switching through the selector circuit that can reconfigure connections between the composite terminal and individual chip data terminals based on testing requirements. This dynamic reconfiguration capability allows the same physical terminal structure to adaptively serve different chips and data paths, enabling flexible parallel testing without requiring dedicated static wirings for each chip.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a plurality of data input/output terminals, a plurality of signal paths for writing data supplied to the data input/output terminals to the memory cell array in parallel, a plurality of latch circuits temporarily holding the data on the signal paths, respectively, and a selector selectively supplying the data to the latch circuits from a test data terminal during a test operation. The data can be thereby supplied from the test data terminal to the latch circuits in parallel during the test operation. The number of terminals used at an operation test can be, therefore, greatly decreased.